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Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extens
From: |
Alistair Francis |
Subject: |
Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension |
Date: |
Tue, 21 Jan 2020 21:11:51 +1000 |
On Wed, Jan 8, 2020 at 12:07 PM Palmer Dabbelt <address@hidden> wrote:
>
> On Mon, 09 Dec 2019 10:11:24 PST (-0800), Alistair Francis wrote:
> > Signed-off-by: Alistair Francis <address@hidden>
> > ---
> > target/riscv/csr.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index a4b598d49a..fc38c45a7e 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -449,6 +449,9 @@ static int read_mideleg(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
> > {
> > env->mideleg = (env->mideleg & ~delegable_ints) | (val &
> > delegable_ints);
> > + if (riscv_has_ext(env, RVH)) {
> > + env->mideleg |= VS_MODE_INTERRUPTS;
> > + }
> > return 0;
> > }
>
> Do you have any idea why? The spec is explicit that this is the case, but I'm
> surprised.
I'm not sure why, maybe to simplfy hardware design?
Alistair
>
> Reviewed-by: Palmer Dabbelt <address@hidden>