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[PATCH v3 0/4] RISC-V: support vector extension part 1
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 0/4] RISC-V: support vector extension part 1 |
Date: |
Fri, 3 Jan 2020 11:33:43 +0800 |
This is the first part of v3 patchset. The changelog of v3 is only coverd
the part1.
Features:
* support specification riscv-v-spec-0.7.1.
* support basic vector extension.
* support Zvlsseg.
* support Zvamo.
* not support Zvediv as it is changing.
* fixed SLEN 128bit.
* element width support 8bit, 16bit, 32bit, 64bit.
Changelog:
v3
* support VLEN configure from qemu command line.
* support ELEN configure from qemu command line.
* support vector specification version configure from qemu command line.
* only default on for "any" cpu, others turn on from command line.
* use a continous memory block for vector register description.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (4):
RISC-V: add vector extension field in CPURISCVState
RISC-V: configure and turn on vector extension from command line
RISC-V: support vector extension csr
RISC-V: add vector extension configure instruction
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.c | 43 +++++++++++-
target/riscv/cpu.h | 77 ++++++++++++++++++---
target/riscv/cpu_bits.h | 15 ++++
target/riscv/csr.c | 92 +++++++++++++++++--------
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 52 ++++++++++++++
target/riscv/translate.c | 17 ++++-
target/riscv/vector_helper.c | 51 ++++++++++++++
10 files changed, 314 insertions(+), 42 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
create mode 100644 target/riscv/vector_helper.c
--
2.23.0
- [PATCH v3 0/4] RISC-V: support vector extension part 1,
LIU Zhiwei <=