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[PATCH v2 12/27] target/riscv: Add virtual register swapping function
From: |
Alistair Francis |
Subject: |
[PATCH v2 12/27] target/riscv: Add virtual register swapping function |
Date: |
Fri, 25 Oct 2019 16:23:50 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 13 +++++-
target/riscv/cpu_bits.h | 7 ++++
target/riscv/cpu_helper.c | 88 +++++++++++++++++++++++++++++++++++++++
3 files changed, 107 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5b71ee416f..0ea56f9059 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -125,6 +125,8 @@ struct CPURISCVState {
target_ulong *mstatus;
target_ulong mip;
+ target_ulong mip_novirt;
+
uint32_t miclaim;
target_ulong *mie;
@@ -161,7 +163,7 @@ struct CPURISCVState {
/* Virtual CSRs */
target_ulong vsstatus;
- uint32_t vsip;
+ target_ulong vsip;
target_ulong vsie;
target_ulong vstvec;
target_ulong vsscratch;
@@ -170,6 +172,14 @@ struct CPURISCVState {
target_ulong vstval;
target_ulong vsatp;
+ /* HS Backup CSRs */
+ target_ulong stvec_hs;
+ target_ulong sscratch_hs;
+ target_ulong sepc_hs;
+ target_ulong scause_hs;
+ target_ulong stval_hs;
+ target_ulong satp_hs;
+
target_ulong scounteren;
target_ulong mcounteren;
@@ -300,6 +310,7 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 95909f159a..d66a29bdb1 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -553,4 +553,11 @@
#define SIP_STIP MIP_STIP
#define SIP_SEIP MIP_SEIP
+/* MIE masks */
+#define MIE_SEIE (1 << IRQ_S_EXT)
+#define MIE_UEIE (1 << IRQ_U_EXT)
+#define MIE_STIE (1 << IRQ_S_TIMER)
+#define MIE_UTIE (1 << IRQ_U_TIMER)
+#define MIE_SSIE (1 << IRQ_S_SOFT)
+#define MIE_USIE (1 << IRQ_U_SOFT)
#endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 21d049cdce..12a10e8679 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -82,6 +82,94 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
+{
+ RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
+ uint32_t tmp;
+ target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+ MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
+ target_ulong sie_mask = MIE_SEIE | MIE_STIE | MIE_SSIE |
+ MIE_UEIE | MIE_UTIE | MIE_USIE;
+ target_ulong mip_mask = MIP_SSIP | MIP_STIP | MIP_SEIP;
+ bool current_virt = riscv_cpu_virt_enabled(env);
+
+ g_assert(riscv_has_ext(env, RVH));
+
+#if defined(TARGET_RISCV64)
+ mstatus_mask |= MSTATUS64_UXL;
+#endif
+
+ if (current_virt) {
+ /* Current V=1 and we are about to change to V=0 */
+ env->mstatus = &env->mstatus_novirt;
+ *env->mstatus &= mstatus_mask;
+ *env->mstatus |= env->vsstatus & ~mstatus_mask;
+ /* Ensure that vsstatus only holds the correct bits */
+ env->vsstatus &= mstatus_mask;
+
+ env->mie = &env->mie_novirt;
+ *env->mie &= sie_mask;
+ *env->mie |= env->vsie & ~sie_mask;
+ /* Ensure that vsie only holds the correct bits */
+ env->vsie &= sie_mask;
+
+ env->vstvec = env->stvec;
+ env->stvec = env->stvec_hs;
+
+ env->vsscratch = env->sscratch;
+ env->sscratch = env->sscratch_hs;
+
+ env->vsepc = env->sepc;
+ env->sepc = env->sepc_hs;
+
+ env->vscause = env->scause;
+ env->scause = env->scause_hs;
+
+ env->vstval = env->sbadaddr;
+ env->sbadaddr = env->stval_hs;
+
+ env->vsatp = env->satp;
+ env->satp = env->satp_hs;
+
+ tmp = env->mip_novirt;
+ tmp = riscv_cpu_update_mip(cpu, mip_mask, tmp);
+ tmp &= mip_mask;
+ env->vsip = tmp;
+ } else {
+ /* Current V=0 and we are about to change to V=1 */
+ env->mstatus = &env->vsstatus;
+ *env->mstatus &= mstatus_mask;
+ *env->mstatus |= env->mstatus_novirt & ~mstatus_mask;
+
+ env->mie = &env->vsie;
+ *env->mie &= sie_mask;
+ *env->mie |= env->mie_novirt & ~sie_mask;
+
+ env->stvec_hs = env->stvec;
+ env->stvec = env->vstvec;
+
+ env->sscratch_hs = env->sscratch;
+ env->sscratch = env->vsscratch;
+
+ env->sepc_hs = env->sepc;
+ env->sepc = env->vsepc;
+
+ env->scause_hs = env->scause;
+ env->scause = env->vscause;
+
+ env->stval_hs = env->sbadaddr;
+ env->sbadaddr = env->vstval;
+
+ env->satp_hs = env->satp;
+ env->satp = env->vsatp;
+
+ tmp = env->vsip;
+ tmp = riscv_cpu_update_mip(cpu, mip_mask, tmp);
+ tmp &= mip_mask;
+ env->mip_novirt = tmp;
+ }
+}
+
bool riscv_cpu_virt_enabled(CPURISCVState *env)
{
if (!riscv_has_ext(env, RVH)) {
--
2.23.0
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, (continued)
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/10/25
- [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/10/25
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25
- [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/10/25
- [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/10/25
- [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/10/25
- [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/10/25
- [PATCH v2 12/27] target/riscv: Add virtual register swapping function,
Alistair Francis <=
- [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/10/25
- [PATCH v2 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/10/25
- [PATCH v2 24/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/10/25
- [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/10/25
- [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/10/25
- [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/10/25
- [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/10/25