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Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR
From: |
Richard Henderson |
Subject: |
Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR |
Date: |
Tue, 8 Oct 2019 21:37:11 -0400 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 10/8/19 6:04 PM, Alistair Francis wrote:
> Instead of relying on atomics to access the MIP register let's update
> our helper function to instead just lock the IO mutex thread before
> writing. This follows the same concept as used in PPC for handling
> interrupts
>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
> target/riscv/cpu.c | 5 ++--
> target/riscv/cpu.h | 9 --------
> target/riscv/cpu_helper.c | 48 +++++++++++++++------------------------
> target/riscv/csr.c | 2 +-
> 4 files changed, 21 insertions(+), 43 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR, Alex Bennée, 2019/10/29