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[PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook
From: |
Alistair Francis |
Subject: |
[PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook |
Date: |
Tue, 8 Oct 2019 13:51:46 -0700 |
The do_unassigned_access hook has been deprecated and RISC-V is the last
user of it. Let's instead update the RISC-V implementation to use
do_transaction_failed instead.
After this series I used the 'git grep' regexes in
docs/devel/loads-stores.rst and these are the memory accesses inside
target/riscv:
monitor.c:102: cpu_physical_memory_read(pte_addr, &pte, ptesize);
cpu_helper.c:262: target_ulong pte = address_space_ldl(cs->as, pte_addr,
attrs, &res);
cpu_helper.c:264: target_ulong pte = address_space_ldq(cs->as, pte_addr,
attrs, &res);
translate.c:782: ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
gdbstub.c:328: env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
All of these look safe to me.
v2:
- Rebase on master
Palmer Dabbelt (2):
RISC-V: Handle bus errors in the page table walker
RISC-V: Implement cpu_do_transaction_failed
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 7 +++++--
target/riscv/cpu_helper.c | 23 ++++++++++++++++-------
3 files changed, 22 insertions(+), 10 deletions(-)
--
2.23.0
- [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook,
Alistair Francis <=