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Re: [PATCH v3 3/3] target/riscv: Make the priv register writable by GDB
From: |
Bin Meng |
Subject: |
Re: [PATCH v3 3/3] target/riscv: Make the priv register writable by GDB |
Date: |
Tue, 8 Oct 2019 20:32:30 +0800 |
On Tue, Oct 8, 2019 at 8:20 AM Jonathan Behrens <address@hidden> wrote:
>
> Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures
> that
> the privilege mode is set to one of them. Once support for the H-extension is
> added, this code will also need to properly update the virtualization status
> when switching between VU/VS-modes and M-mode.
>
> Signed-off-by: Jonathan Behrens <address@hidden>
> ---
> target/riscv/gdbstub.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>