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Re: [PATCH v2] target/riscv: Expose "priv" register for GDB
From: |
Bin Meng |
Subject: |
Re: [PATCH v2] target/riscv: Expose "priv" register for GDB |
Date: |
Sat, 5 Oct 2019 20:08:24 +0800 |
On Fri, Oct 4, 2019 at 11:18 PM Jonathan Behrens <address@hidden> wrote:
>
> This patch enables a debugger to read and write the current privilege level
> via
> a special "priv" register. When compiled with CONFIG_USER_ONLY the register is
> still visible but is hardwired to zero.
>
> Signed-off-by: Jonathan Behrens <address@hidden>
> ---
> gdb-xml/riscv-32bit-cpu.xml | 1 +
> gdb-xml/riscv-64bit-cpu.xml | 1 +
> target/riscv/cpu.c | 2 +-
> target/riscv/gdbstub.c | 14 ++++++++++++++
> 4 files changed, 17 insertions(+), 1 deletion(-)
> ---
> Changelog V2:
> - Use PRV_H and PRV_S instead of integer literals
>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>