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Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1,
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 |
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Date: |
Thu, 19 Sep 2019 13:26:56 +0100 |
On Wed, 18 Sep 2019 at 16:27, Palmer Dabbelt <address@hidden> wrote:
>
> The following changes since commit f8c3db33a5e863291182f8862ddf81618a7c6194:
>
> target/sparc: Switch to do_transaction_failed() hook (2019-09-17 12:01:00
> +0100)
>
> are available in the Git repository at:
>
> git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1-v3
>
> for you to fetch changes up to b3e86929189c526d22ef49e18f2f5066535f6deb:
>
> gdbstub: riscv: fix the fflags registers (2019-09-17 08:42:50 -0700)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3
>
> This contains quite a few patches that I'd like to target for 4.2.
> They're mostly emulation fixes for the sifive_u board, which now much
> more closely matches the hardware and can therefor run the same fireware
> as what gets loaded onto the board. Additional user-visible
> improvements include:
>
> * support for loading initrd files from the command line into Linux, via
> /chosen/linux,initrd-{start,end} device tree nodes.
> * The conversion of LOG_TRACE to trace events.
> * The addition of clock DT nodes for our uart and ethernet.
>
> This also includes some preliminary work for the H extension patches,
> but does not include the H extension patches as I haven't had time to
> review them yet.
>
> This passes my OE boot test on 32-bit and 64-bit virt machines, as well
> as a 64-bit upstream Linux boot on the sifive_u machine. It has been
> fixed to actually pass "make check" this time.
>
> Changes since v2 (never made it to the list):
>
> * Sets the sifive_u machine default core count to 2 instead of 5.
>
> Changes since v1 <address@hidden>:
>
> * Sets the sifive_u machine default core count to 5 instead of 1, as
> it's impossible to have a single core sifive_u machine.
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.
-- PMM
- [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, (continued)
- [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 45/48] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 42/48] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 46/48] target/riscv: Fix mstatus dirty mask, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 48/48] gdbstub: riscv: fix the fflags registers, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 10/48] riscv: Add a helper routine for finding firmware, Palmer Dabbelt, 2019/09/18
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3,
Peter Maydell <=