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[Qemu-riscv] [PULL 11/48] riscv: Resolve full path of the given bios ima
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 11/48] riscv: Resolve full path of the given bios image |
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Date: |
Wed, 18 Sep 2019 07:56:03 -0700 |
From: Bin Meng <address@hidden>
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/boot.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 10f7991490..2e92fb0680 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -72,14 +72,14 @@ void riscv_find_and_load_firmware(MachineState *machine,
firmware_filename = riscv_find_firmware(default_machine_firmware);
} else {
firmware_filename = machine->firmware;
+ if (strcmp(firmware_filename, "none")) {
+ firmware_filename = riscv_find_firmware(firmware_filename);
+ }
}
if (strcmp(firmware_filename, "none")) {
/* If not "none" load the firmware */
riscv_load_firmware(firmware_filename, firmware_load_addr);
- }
-
- if (!strcmp(machine->firmware, "default")) {
g_free(firmware_filename);
}
}
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 01/48] riscv: sifive_u: Add support for loading initrd, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 03/48] riscv: sifive_u: Fix clock-names property for ethernet node, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 06/48] riscv: plic: Remove unused interrupt functions, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 07/48] target/riscv: Create function to test if FP is enabled, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 11/48] riscv: Resolve full path of the given bios image,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 13/48] riscv: sifive_test: Add reset functionality, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 18/48] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/18