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[Qemu-riscv] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes |
Date: |
Fri, 6 Sep 2019 09:20:11 -0700 |
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 7 ++++---
include/hw/riscv/sifive_u_prci.h | 10 ++++++++++
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ff2e28e..ea21095 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -78,7 +78,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
int cpu;
uint32_t *cells;
char *nodename;
- char ethclk_names[] = "pclk\0hclk\0tx_clk";
+ char ethclk_names[] = "pclk\0hclk";
uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
uint32_t uartclk_phandle;
uint32_t hfclk_phandle, rtcclk_phandle;
@@ -263,7 +263,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
- ethclk_phandle, ethclk_phandle, ethclk_phandle);
+ prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
sizeof(ethclk_names));
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
@@ -293,7 +293,8 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_UART0].base,
0x0, memmap[SIFIVE_U_UART0].size);
- qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h
index 60a2eab..0a531fd 100644
--- a/include/hw/riscv/sifive_u_prci.h
+++ b/include/hw/riscv/sifive_u_prci.h
@@ -78,4 +78,14 @@ typedef struct SiFiveUPRCIState {
uint32_t clkmuxstatus;
} SiFiveUPRCIState;
+/*
+ * Clock indexes for use by Device Tree data and the PRCI driver.
+ *
+ * These values are from sifive-fu540-prci.h in the Linux kernel.
+ */
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
#endif /* HW_SIFIVE_U_PRCI_H */
--
2.7.4
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, (continued)
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/14
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Jonathan Behrens, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/16
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Alistair Francis, 2019/09/16
[Qemu-riscv] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 23/32] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 26/32] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes,
Bin Meng <=
[Qemu-riscv] [PATCH v8 25/32] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 29/32] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 32/32] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 28/32] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 30/32] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/09/06
[Qemu-riscv] [PATCH v8 27/32] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/09/06