[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extens
|
From: |
Richard Henderson |
|
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1 |
|
Date: |
Tue, 3 Sep 2019 07:21:10 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 9/2/19 2:43 AM, liuzhiwei wrote:
>> This is most definitely not the correct way to implement first-fault.
>>
>> You need to have a look at target/arm/sve_helper.c, e.g. sve_ldff1_r,
>> where we test pages for validity with tlb_vaddr_to_host.
> Why should test pages for validity? If there is a page fault in running time,
> it just the case why it must use the fault-only-first instruction.
So that the helper does not fault for the Nth access, N > 1.
You test to see if the page has a mapping, and if it doesn't,
you end the instruction, without going through the exception
path that I have objections to.
Except for gather loads, you don't have to test for every
access, only at page boundaries. And then you may also arrange
to use direct host access to the pages that you've validated.
Again, have a look at sve_ldff1_r.
> A single array is a good idea. But vreg[] will be better for understanding as
> it preserve the register concepts.
A function access to the registers would be just as good for that.
r~