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[Qemu-riscv] [PATCH v6 23/30] riscv: sifive_u: Update UART base addresse
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v6 23/30] riscv: sifive_u: Update UART base addresses and IRQs |
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Date: |
Tue, 27 Aug 2019 07:58:32 -0700 |
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- update IRQ numbers of both UARTs to match hardware as well
Changes in v2: None
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3b1fe46..c7b9f96 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -62,8 +62,8 @@ static const struct MemmapEntry {
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
- [SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
+ [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
};
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 2a023be..b41e730 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -64,8 +64,8 @@ enum {
};
enum {
- SIFIVE_U_UART0_IRQ = 3,
- SIFIVE_U_UART1_IRQ = 4,
+ SIFIVE_U_UART0_IRQ = 4,
+ SIFIVE_U_UART1_IRQ = 5,
SIFIVE_U_GEM_IRQ = 0x35
};
--
2.7.4
- [Qemu-riscv] [PATCH v6 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, (continued)
- [Qemu-riscv] [PATCH v6 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 24/30] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 16/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 23/30] riscv: sifive_u: Update UART base addresses and IRQs,
Bin Meng <=
- [Qemu-riscv] [PATCH v6 30/30] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 21/30] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 28/30] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 19/30] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 25/30] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/08/27