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[Qemu-riscv] [PATCH v6 10/30] riscv: sifive_e: prci: Fix a typo of hfxos
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v6 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming |
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Date: |
Tue, 27 Aug 2019 07:58:19 -0700 |
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_e_prci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index c514032..71de089 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -90,7 +90,7 @@ static void sifive_e_prci_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
- s->hfxosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN);
+ s->hfxosccfg = (SIFIVE_E_PRCI_HFXOSCCFG_RDY | SIFIVE_E_PRCI_HFXOSCCFG_EN);
s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS |
SIFIVE_E_PRCI_PLLCFG_LOCK);
s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1;
--
2.7.4
- [Qemu-riscv] [PATCH v6 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 01/30] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 03/30] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 04/30] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 08/30] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 07/30] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming,
Bin Meng <=
- [Qemu-riscv] [PATCH v6 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 12/30] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 24/30] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 16/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/27
- [Qemu-riscv] [PATCH v6 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/27