Re: [Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the

From:	Jim Wilson
Subject:	Re: [Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
Date:	Fri, 23 Aug 2019 15:44:34 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0

On 8/21/19 9:28 AM, Georg Kotheimer wrote:

The size of the FPU registers depends solely on the floating point
extensions supported by the target architecture.
However, in the previous implementation the floating point register
size was derived from whether the target architecture is 32-bit or
64-bit.

To allow RVF without RVD, changes to riscv_gdb_get_fpu() and
riscv_gdb_set_fpu() were necessary.


Reviewed-by: Jim Wilson <address@hidden>

Jim

[Prev in Thread]

Current Thread

[Next in Thread]

[Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions, Georg Kotheimer, 2019/08/21
- Re: [Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions, Jim Wilson <=
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions, Alistair Francis, 2019/08/23

Prev by Date: [Qemu-riscv] [Qemu-devel] [PATCH 3/9] exec: Replace DEVICE_LITTLE_ENDIAN with MO_LE
Next by Date: [Qemu-riscv] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension
Previous by thread: [Qemu-riscv] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
Next by thread: Re: [Qemu-riscv] [Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions
Index(es):
- Date
- Thread