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Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unn
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h |
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Date: |
Fri, 23 Aug 2019 10:38:13 -0700 |
On Thu, Aug 22, 2019 at 10:21 PM Bin Meng <address@hidden> wrote:
>
> The inclusion of "target/riscv/cpu.h" is unnecessary in various
> sifive model drivers.
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
>
> ---
>
> Changes in v5:
> - new patch to remove the unnecessary include of target/riscv/cpu.h
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> hw/riscv/sifive_prci.c | 1 -
> hw/riscv/sifive_test.c | 1 -
> hw/riscv/sifive_uart.c | 1 -
> 3 files changed, 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
> index 1ab98d4..1957dcd 100644
> --- a/hw/riscv/sifive_prci.c
> +++ b/hw/riscv/sifive_prci.c
> @@ -22,7 +22,6 @@
> #include "hw/sysbus.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> -#include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_prci.h"
>
> static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int
> size)
> diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
> index 655a3d7..31cad9f 100644
> --- a/hw/riscv/sifive_test.c
> +++ b/hw/riscv/sifive_test.c
> @@ -23,7 +23,6 @@
> #include "qemu/log.h"
> #include "qemu/module.h"
> #include "sysemu/sysemu.h"
> -#include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_test.h"
>
> static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int
> size)
> diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
> index cd74043..1601bd9 100644
> --- a/hw/riscv/sifive_uart.c
> +++ b/hw/riscv/sifive_uart.c
> @@ -22,7 +22,6 @@
> #include "hw/sysbus.h"
> #include "chardev/char.h"
> #include "chardev/char-fe.h"
> -#include "target/riscv/cpu.h"
> #include "hw/riscv/sifive_uart.h"
>
> /*
> --
> 2.7.4
>
>
- [Qemu-riscv] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/08/23
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h,
Alistair Francis <=
- [Qemu-riscv] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/23