Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Select FPU gdb xml file based on the supported extensions

[Georg Kotheimer]

> While this appears reasonable, I wonder if RVF w/o RVD actually works?
>
> Examining the two get/set functions, they always transfer 64 bits for the fpu
> registers.

Wouldn't that implicate that FPU debugging has never been working properly on
RV32, as prior to my changes the FPU registers on RV32 were always 32 bits
wide? Nope, it does work (tested with a build not containing my changes), but
for all the wrong reasons. The get/set functions should be modified so that
they take the actual size of the floating point registers into account.


> In addition, there's a suspicious use of sizeof(target_ulong) when 
> transferring
> the fpu related csr registers, which definitely shouldn't work with the shared
> files above.  If the xml file is correct, this should always be uint32_t.

Good catch. According to the RISC-V ISA specification the fcsr is always 32
bit wide.

I did a little bit of investigation and found the following contradiction in
the gdb xml files. The registers fflags/frm/fcsr are listed in general csr
file as well as in the fpu file. For RV64 the bitsize of the two definitions
differs.

gdb-xml/riscv-32bit-csr.xml:
   <reg name="fflags" bitsize="32"/>
   <reg name="frm" bitsize="32"/>
   <reg name="fcsr" bitsize="32"/>

gdb-xml/riscv-64bit-csr.xml:
   <reg name="fflags" bitsize="64"/>
   <reg name="frm" bitsize="64"/>
   <reg name="fcsr" bitsize="64"/>

gdb-xml/riscv-fpu-f.xml: (former riscv-32bit-fpu.xml)
   <reg name="fflags" bitsize="32" type="int" regnum="66"/>
   <reg name="frm" bitsize="32" type="int" regnum="67"/>
   <reg name="fcsr" bitsize="32" type="int" regnum="68"/>

gdb-xml/riscv-fpu-d.xml: (former riscv-64bit-fpu.xml)
   <reg name="fflags" bitsize="32" type="int" regnum="66"/>
   <reg name="frm" bitsize="32" type="int" regnum="67"/>
   <reg name="fcsr" bitsize="32" type="int" regnum="68"/>

I don't know if this is on purpose, but my guess would be that fflags/frm/fcsr
don't belong into riscv-32/64bit-csr.xml, and the bitsize should be 32
regardless of the architecture's bitness.