Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Select FPU gdb xml file based on the supported extensions

[Richard Henderson]

On 7/3/19 4:26 PM, Georg Kotheimer wrote:
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target architecture is 32-bit or
> 64-bit.
> 
...
> -#if defined(TARGET_RISCV32)
> -    if (env->misa & RVF) {
> +
> +    if (env->misa & RVD) {
>          gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> -                                 36, "riscv-32bit-fpu.xml", 0);
> +                                 36, "riscv-fpu-d.xml", 0);
> +    } else if (env->misa & RVF) {
> +        gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> +                                 36, "riscv-fpu-f.xml", 0);
>      }

While this appears reasonable, I wonder if RVF w/o RVD actually works?

Examining the two get/set functions, they always transfer 64 bits for the fpu
registers.

In addition, there's a suspicious use of sizeof(target_ulong) when transferring
the fpu related csr registers, which definitely shouldn't work with the shared
files above.  If the xml file is correct, this should always be uint32_t.


r~