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[Qemu-riscv] [PULL 08/32] RISC-V: Check PMP during Page Table Walks
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 08/32] RISC-V: Check PMP during Page Table Walks |
Date: |
Wed, 3 Jul 2019 01:40:24 -0700 |
From: Hesham Almatary <address@hidden>
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens <address@hidden>
Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 10 +++++++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2e743312536b..934b71c85e13 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@ enum {
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
+#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
#define MMU_USER_IDX 3
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 71b8123b1019..66be83210f11 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -230,6 +230,12 @@ restart:
/* check that physical address of PTE is legal */
target_ulong pte_addr = base + idx * ptesize;
+
+ if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+ !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
+ 1 << MMU_DATA_LOAD, PRV_S)) {
+ return TRANSLATE_PMP_FAIL;
+ }
#if defined(TARGET_RISCV32)
target_ulong pte = ldl_phys(cs->as, pte_addr);
#elif defined(TARGET_RISCV64)
@@ -448,8 +454,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
mode)) {
+ ret = TRANSLATE_PMP_FAIL;
+ }
+ if (ret == TRANSLATE_PMP_FAIL) {
pmp_violation = true;
- ret = TRANSLATE_FAIL;
}
if (ret == TRANSLATE_SUCCESS) {
tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 03/32] target/riscv: Fix PMP range boundary address bug, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 02/32] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 08/32] RISC-V: Check PMP during Page Table Walks,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 13/32] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 15/32] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 18/32] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/07/03