[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v
From: |
Peter Maydell |
Subject: |
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 |
Date: |
Mon, 1 Jul 2019 17:55:59 +0100 |
On Fri, 28 Jun 2019 at 18:32, Palmer Dabbelt <address@hidden> wrote:
>
> merged tag 'mips-queue-jun-21-2019'
> The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde:
>
> Merge remote-tracking branch
> 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21
> 15:40:50 +0100)
>
> are available in the Git repository at:
>
> git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v2
>
> for you to fetch changes up to 56bf43fc565a2fa3e0a618ab45e1c82896d0782a:
>
> hw/riscv: Load OpenSBI as the default firmware (2019-06-28 10:10:30 -0700)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2
>
> This pull request contains a handful of patches that I'd like to target
> for the 4.1 soft freeze. There are a handful of new features:
>
> * The -bios option now works sanely, including both a built-in copy of
> OpenSBI and the ability to load external versions. Users no longer
> need to figure out how to build their own firmware.
> * Support for the 1.11.0, the latest privileged specification.
> * Support for reading and writing the PRCI registers.
> * Better control over the ISA of the target machine.
> * Support for the cpu-topology device tree node.
>
> Additionally, there are a handful of bug fixes including:
>
> * Load reservations are now broken by both store conditional and by
> scheduling, which fixes issues with parallel applications.
> * Various fixes to the PMP implementation.
> * Fixes to the 32-bit linux-user syscall ABI.
> * Various fixes for instruction decodeing.
> * A fix to the PCI device tree "bus-range" property.
>
> This boots 32-bit and 64-bit OpenEmbedded.
>
> Changes since v1 [riscv-for-master-4.1-sf1]:
>
> * Contains a fix to the sifive_u OpenSBI integration.
Hi; I had some comments about the opensbi blobs (and in particular
a question about the licensing), so I'm not going to apply this.
You might want to send a v2 which has everything except the new
blobs, while we figure out what we want to do about them.
thanks
-- PMM
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2,
Peter Maydell <=