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[Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding |
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Date: |
Fri, 28 Jun 2019 10:32:04 -0700 |
From: Bin Meng <address@hidden>
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42d8..487f61404b21 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -298,7 +298,7 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
- memmap[VIRT_PCIE_ECAM].base /
+ memmap[VIRT_PCIE_ECAM].size /
PCIE_MMCFG_SIZE_MIN - 1);
qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg", 0,
memmap[VIRT_PCIE_ECAM].base,
--
2.21.0
- [Qemu-riscv] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props, (continued)
- [Qemu-riscv] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 02/34] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address bug, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 21/34] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 19/34] target/riscv: Remove user version information, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 08/34] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/06/28