Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64

[Palmer Dabbelt]

On Tue, 25 Jun 2019 08:36:28 PDT (-0700), address@hidden wrote:
> On 6/24/19 8:08 PM, Joel Sing wrote:
> > Regarding the alignment for reservations, the
> > specification does require this, although I do not recall seeing any enforcement
> > of this by qemu itself.
>
> Ah, I see it now.  Enforcement begins here:
>
> static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
> {
>     REQUIRE_EXT(ctx, RVA);
>     return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
>                            ^^^^^^^^
>
> This will force softmmu (but notably not linux-user; a design limitation) to
> generate an alignment fault for an unaligned address.

That was probably correct at the time the code went in, as the ISA used to
allow these to succeed but not be atomic.  No implementations did this, so as
part of the ratification process we just mandated that unaligned atomics always
trap.

Is there a better way to fix this than just doing the alignment check
explicitly?