Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding

[Bin Meng]

Hi,

On Fri, Jun 7, 2019 at 2:46 AM Alistair Francis <address@hidden> wrote:
>
> On Thu, Jun 6, 2019 at 5:55 AM Bin Meng <address@hidden> wrote:
> >
> > On Thu, May 30, 2019 at 11:36 AM Bin Meng <address@hidden> wrote:
> > >
> > > Hi Alistair,
> > >
> > > On Thu, May 30, 2019 at 11:14 AM Alistair Francis <address@hidden> wrote:
> > > >
> > > > On Wed, May 29, 2019 at 1:52 AM Bin Meng <address@hidden> wrote:
> > > > >
> > > > > The largest pci bus number should be calculated from ECAM size,
> > > > > instead of its base address.
> > > > >
> > > > > Signed-off-by: Bin Meng <address@hidden>
> > > >
> > > > This seems ok, can you maybe explain what this fixes?
> > > >
> > >
> > > The logic is wrong, as the commit message said. With current wrong
> > > logic, the largest pci bus number encoded in "bus-ranges" property was
> > > wrongly set to 0x2ff in this case. Per pci spec, the bus number should
> > > not exceed 0xff.
> > >
> >
> > Ping?
>
> Reviewed-by: Alistair Francis <address@hidden>

Can this go in the 4.1 PR?

Regards,
Bin