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[Qemu-riscv] [PATCH v1 20/27] target/riscv: Disable guest FP support bas
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status |
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Date: |
Fri, 7 Jun 2019 14:56:23 -0700 |
When the Hypervisor extension is in use we only enable floating point
support when both status and bsstatus have enabled floating point
support.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d1f73396e4..b009049cc4 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -193,6 +193,9 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool
enable)
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
+ if (riscv_cpu_virt_enabled(env) && !(env->bsstatus & MSTATUS_FS)) {
+ return false;
+ }
return true;
}
--
2.21.0
- [Qemu-riscv] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions, (continued)
- [Qemu-riscv] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 25/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/06/07