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[Qemu-riscv] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for fl
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops |
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Date: |
Fri, 7 Jun 2019 14:56:29 -0700 |
Respect the contents of MSTATUS.MPRV and HSTATUS.SPRV when performing
floating point operations when V=0.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/translate.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1c3cd1c94b..d4fa7d056d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -765,7 +765,21 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
- ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+ if (riscv_has_ext(env, RVH)) {
+ ctx->virt_enabled = riscv_cpu_virt_enabled(env);
+ if (env->priv_ver == PRV_M &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ get_field(env->mstatus, MSTATUS_MPV)) {
+ ctx->virt_enabled = true;
+ } else if (env->priv == PRV_S &&
+ !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_SPRV) &&
+ get_field(env->hstatus, HSTATUS_SPV)) {
+ ctx->virt_enabled = true;
+ }
+ } else {
+ ctx->virt_enabled = false;
+ }
#else
ctx->virt_enabled = false;
#endif
--
2.21.0
- [Qemu-riscv] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions, (continued)
- [Qemu-riscv] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 12/27] target/riscv: Add background register swapping function, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 25/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/06/07