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[Qemu-riscv] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled |
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Date: |
Fri, 7 Jun 2019 14:55:35 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d1378bb7f..6111f0f0bc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -220,14 +220,41 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstatus ", env->bsstatus);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ",
(target_ulong)atomic_read(&env->mip));
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bsip ",
+ (target_ulong)atomic_read(&env->bsip));
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bsie ", env->bsie);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bstvec ", env->bstvec);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bsepc ", env->bsepc);
+ }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "bscause ", env->bscause);
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.21.0
- [Qemu-riscv] [PATCH v1 00/27] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 03/27] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 12/27] target/riscv: Add background register swapping function, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/06/07