[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PULL 25/29] target/riscv: Add the HSTATUS register masks
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 25/29] target/riscv: Add the HSTATUS register masks |
Date: |
Sat, 25 May 2019 18:09:44 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviwed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_bits.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 52c21699774f..a179137bc1f2 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -382,6 +382,24 @@
#define SSTATUS_SD SSTATUS64_SD
#endif
+/* hstatus CSR bits */
+#define HSTATUS_SPRV 0x00000001
+#define HSTATUS_STL 0x00000040
+#define HSTATUS_SPV 0x00000080
+#define HSTATUS_SP2P 0x00000100
+#define HSTATUS_SP2V 0x00000200
+#define HSTATUS_VTVM 0x00100000
+#define HSTATUS_VTSR 0x00400000
+
+#define HSTATUS32_WPRI 0xFF8FF87E
+#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
+
+#if defined(TARGET_RISCV32)
+#define HSTATUS_WPRI HSTATUS32_WPRI
+#elif defined(TARGET_RISCV64)
+#define HSTATUS_WPRI HSTATUS64_WPRI
+#endif
+
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 25/29] target/riscv: Add the HSTATUS register masks,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 26/29] target/riscv: Add the HGATP register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 24/29] target/riscv: Add Hypervisor CSR macros, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved, Palmer Dabbelt, 2019/05/25