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Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SA
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes |
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Date: |
Wed, 8 May 2019 10:47:53 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 5/8/19 10:38 AM, Jonathan Behrens wrote:
> There is an analogous change for ARM here:
> https://patchwork.kernel.org/patch/10649857
>
> Signed-off-by: Jonathan Behrens <address@hidden>
> ---
> target/riscv/csr.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <address@hidden>
r~