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[Qemu-riscv] [PATCH v1 8/8] target/riscv: Add the HGATP register masks
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 8/8] target/riscv: Add the HGATP register masks |
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Date: |
Sat, 20 Apr 2019 02:27:43 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_bits.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a179137bc1..dc9d53d4be 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -208,6 +208,17 @@
#define CSR_HIDELEG 0xa03
#define CSR_HGATP 0xa80
+#if defined(TARGET_RISCV32)
+#define HGATP_MODE SATP32_MODE
+#define HGATP_ASID SATP32_ASID
+#define HGATP_PPN SATP32_PPN
+#endif
+#if defined(TARGET_RISCV64)
+#define HGATP_MODE SATP64_MODE
+#define HGATP_ASID SATP64_ASID
+#define HGATP_PPN SATP64_PPN
+#endif
+
/* Performance Counters */
#define CSR_MHPMCOUNTER3 0xb03
#define CSR_MHPMCOUNTER4 0xb04
--
2.21.0
- [Qemu-riscv] [PATCH v1 0/8] RISC-V: Add some prep patches for the Hypervisor, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 1/8] target/riscv: Mark privilege level 2 as reserved, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 2/8] target/riscv: Trigger interrupt on MIP update asynchronously, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 3/8] target/riscv: Improve the scause logic, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 5/8] target/riscv: Allow setting mstatus virtulisation bits, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 4/8] target/riscv: Add the MPV and MTL mstatus bits, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 6/8] target/riscv: Add Hypervisor CSR macros, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 7/8] target/riscv: Add the HSTATUS register masks, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 8/8] target/riscv: Add the HGATP register masks,
Alistair Francis <=