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[Qemu-riscv] [PATCH v1 3/8] target/riscv: Improve the scause logic
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 3/8] target/riscv: Improve the scause logic |
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Date: |
Sat, 20 Apr 2019 02:27:02 +0000 |
No functional change, just making the code easier to read.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 582d58aad9..e7d9dd95cc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -525,7 +525,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- env->scause = cause | ~(((target_ulong)-1) >> async);
+ env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
env->sepc = env->pc;
env->sbadaddr = tval;
env->pc = (env->stvec >> 2 << 2) +
--
2.21.0
- [Qemu-riscv] [PATCH v1 0/8] RISC-V: Add some prep patches for the Hypervisor, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 1/8] target/riscv: Mark privilege level 2 as reserved, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 2/8] target/riscv: Trigger interrupt on MIP update asynchronously, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 3/8] target/riscv: Improve the scause logic,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 5/8] target/riscv: Allow setting mstatus virtulisation bits, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 4/8] target/riscv: Add the MPV and MTL mstatus bits, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 6/8] target/riscv: Add Hypervisor CSR macros, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 7/8] target/riscv: Add the HSTATUS register masks, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 8/8] target/riscv: Add the HGATP register masks, Alistair Francis, 2019/04/19