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[Qemu-riscv] [PATCH v1 0/6] RISC-V: Add properties to the CPUs


From: Alistair Francis
Subject: [Qemu-riscv] [PATCH v1 0/6] RISC-V: Add properties to the CPUs
Date: Sat, 20 Apr 2019 02:23:36 +0000

This series is based on the previous "RISC-V: Allow specifying CPU ISA
via command line" series. This series does not allow custom ISA
extensions instead it just allows other property setting.

This series allows users to specify spec versions, MMU support and PMP
support from the command line.

This series depreates some existing CPUs and machines as they are no
longer required.

Alistair Francis (6):
  linux-user/riscv: Add the CPU type as a comment
  riscv: virt: Allow specifying a CPU via commandline
  target/riscv: Create settable CPU properties
  target/riscv: Add a base 32 and 64 bit CPU
  target/riscv: Deprecate the generic no MMU CPUs
  riscv: spike: Add a generic spike machine

 hw/riscv/spike.c              | 106 +++++++++++++++++++++++++++++++++-
 hw/riscv/virt.c               |   3 +-
 include/hw/riscv/virt.h       |   4 +-
 linux-user/riscv/target_elf.h |   1 +
 qemu-deprecated.texi          |  21 +++++++
 target/riscv/cpu.c            |  63 ++++++++++++++++++++
 target/riscv/cpu.h            |  10 ++++
 7 files changed, 204 insertions(+), 4 deletions(-)

-- 
2.21.0


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