Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU

[Ian Campbell]

On Fri, 2019-03-29 at 22:39 +0000, Alistair Francis wrote:
> +    for (i = 0; i < strlen(riscv_cpu); i++) {
> +        if (i == 0 && riscv_cpu[i] == 'r' &&
> +            riscv_cpu[i + 1] == 'v') {

Dpes something somewhere else enforce a minimum length or can
`riscv_cpu[i + 1]` be past the end of the string?

Similarly some more times below and also for the `i += 2` bits.

> +            /* Starts with "rv" */
> +            i += 2;
> +            if (riscv_cpu[i] == '3' && riscv_cpu[i + 1] == '2') {
> +                i += 2;
> +                valid = true;
> +                rvxlen = RV32;
> +            }
> +            if (riscv_cpu[i] == '6' && riscv_cpu[i + 1] == '4') {
> +                i += 2;
> +                valid = true;
> +                rvxlen = RV64;
> +            }
> +        }

Ian.