[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PULL 04/19] RISC-V: Add debug support for accessing CSRs.
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 04/19] RISC-V: Add debug support for accessing CSRs. |
Date: |
Tue, 19 Mar 2019 05:47:48 -0700 |
From: Jim Wilson <address@hidden>
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 5 +++++
target/riscv/csr.c | 32 +++++++++++++++++++++++++-------
2 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5c2aebf13251..4c5de30b3721 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -172,6 +172,9 @@ struct CPURISCVState {
/* physical memory protection */
pmp_table_t pmp_state;
+
+ /* True if in debugger mode. */
+ bool debugger;
#endif
float_status fp_status;
@@ -293,6 +296,8 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
target_ulong *pc,
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
+int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask);
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
target_ulong val)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 960d2b0aa951..9a40b4c7baed 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static int fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -92,7 +92,7 @@ static int pmp(CPURISCVState *env, int csrno)
static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -103,7 +103,7 @@ static int read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -115,7 +115,7 @@ static int write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -126,7 +126,7 @@ static int read_frm(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -138,7 +138,7 @@ static int write_frm(CPURISCVState *env, int csrno,
target_ulong val)
static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -150,7 +150,7 @@ static int read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -827,6 +827,24 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
return 0;
}
+/*
+ * Debugger support. If not in user mode, set env->debugger before the
+ * riscv_csrrw call and clear it after the call.
+ */
+int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret;
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = true;
+#endif
+ ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = false;
+#endif
+ return ret;
+}
+
/* Control and Status Register function table */
static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
--
2.19.2
- [Qemu-riscv] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, (continued)
- [Qemu-riscv] [PULL 15/19] RISC-V: Update load reservation comment in do_interrupt, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 14/19] RISC-V: Convert trap debugging to trace events, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 13/19] RISC-V: Add support for vectored interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 12/19] RISC-V: Change local interrupts from edge to level, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 11/19] RISC-V: linux-user support for RVE ABI, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 10/19] elf: Add RISC-V PSABI ELF header defines, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 09/19] RISC-V: Remove unnecessary disassembler constraints, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 05/19] RISC-V: Add hooks to use the gdb xml files., Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 08/19] RISC-V: Allow interrupt controllers to claim interrupts, Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 04/19] RISC-V: Add debug support for accessing CSRs.,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 03/19] RISC-V: Fixes to CSR_* register macros., Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 02/19] RISC-V: Add 64-bit gdb xml files., Palmer Dabbelt, 2019/03/19
- [Qemu-riscv] [PULL 01/19] RISC-V: Add 32-bit gdb xml files., Palmer Dabbelt, 2019/03/19
- Re: [Qemu-riscv] [PULL] RISC-V Patches for 4.0-rc0, Part 2, Peter Maydell, 2019/03/19