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[Qemu-riscv] [PULL 19/34] target/riscv: Remove gen_jalr()
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 19/34] target/riscv: Remove gen_jalr() |
Date: |
Fri, 1 Mar 2019 13:49:30 -0800 |
From: Bastian Koppelmann <address@hidden>
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
target/riscv/translate.c | 38 -------------------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 4a23372cb823..631a88906bce 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
- gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
+ /* no chaining with JALR */
+ TCGLabel *misaligned = NULL;
+ TCGv t0 = tcg_temp_new();
+
+
+ gen_get_gpr(cpu_pc, a->rs1);
+ tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+ tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+
+ if (!has_ext(ctx, RVC)) {
+ misaligned = gen_new_label();
+ tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+ }
+
+ if (a->rd != 0) {
+ tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
+ }
+ tcg_gen_lookup_and_goto_ptr();
+
+ if (misaligned) {
+ gen_set_label(misaligned);
+ gen_exception_inst_addr_mis(ctx);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(t0);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 80afa2c1e62b..9dee2ec24287 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -531,44 +531,6 @@ static void gen_jal(DisasContext *ctx, int rd,
target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- target_long imm)
-{
- /* no chaining with JALR */
- TCGLabel *misaligned = NULL;
- TCGv t0 = tcg_temp_new();
-
- switch (opc) {
- case OPC_RISC_JALR:
- gen_get_gpr(cpu_pc, rs1);
- tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
- tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-
- if (!has_ext(ctx, RVC)) {
- misaligned = gen_new_label();
- tcg_gen_andi_tl(t0, cpu_pc, 0x2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
- }
-
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
- tcg_gen_lookup_and_goto_ptr();
-
- if (misaligned) {
- gen_set_label(misaligned);
- gen_exception_inst_addr_mis(ctx);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
- tcg_temp_free(t0);
-}
-
static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long bimm)
{
--
2.18.1
- [Qemu-riscv] [PULL 12/34] target/riscv: Convert RV64F insns to decodetree, (continued)
- [Qemu-riscv] [PULL 12/34] target/riscv: Convert RV64F insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 15/34] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 21/34] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 22/34] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 26/34] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 11/34] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 29/34] target/riscv: Remove decode_RV32_64G(), Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 25/34] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 19/34] target/riscv: Remove gen_jalr(),
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 14/34] target/riscv: Convert RV64D insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 28/34] target/riscv: Remove gen_system(), Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 30/34] target/riscv: Convert @cs_2 insns to share translation functions, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 13/34] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Palmer Dabbelt, 2019/03/01