qemu-riscv (thread)

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qemu-riscv (thread)

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Last Modified: Thu Feb 28 2019 10:04:33 -0500
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[Qemu-riscv] Add proper alignment check and pending 'C' extension for riscv, amagdy . afifi, 2019/02/22
- [Qemu-riscv] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, amagdy . afifi, 2019/02/22
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Richard Henderson, 2019/02/22
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Amed Magdy, 2019/02/24
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Richard Henderson, 2019/02/24
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Amed Magdy, 2019/02/26
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Amed Magdy, 2019/02/26
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Eric Blake, 2019/02/23
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Amed Magdy, 2019/02/24
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes, Eric Blake, 2019/02/25
[Qemu-riscv] [PATCH v8 00/34] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 15/34] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 08/34] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 14/34] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 07/34] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 03/34] target/riscv: Convert RV32I load/store insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 04/34] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 11/34] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 09/34] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 10/34] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 27/34] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 29/34] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 19/34] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 06/34] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 12/34] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 28/34] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 13/34] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 30/34] target/riscv: Convert @cs_2 insns to share translation functions, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/02/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Alistair Francis, 2019/02/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Thomas Huth, 2019/02/28
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Paolo Bonzini, 2019/02/28
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
[Qemu-riscv] [PATCH v2 00/11] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 02/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 03/11] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 05/11] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 01/11] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 04/11] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 06/11] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 07/11] RISC-V: Change local interrupts from edge to level, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 10/11] RISC-V: Update load reservation comment in do_interrupt, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 11/11] riscv: sifive_u: Allow up to 4 CPUs to be created, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 09/11] RISC-V: Convert trap debugging to trace events, Alistair Francis, 2019/02/20
- [Qemu-riscv] [PATCH v2 08/11] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/02/20
[Qemu-riscv] [PATCH v7 00/35] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 04/35] target/riscv: Convert RV32I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 08/35] target/riscv: Convert RVXI csr insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 20/35] target/riscv: Remove gen_jalr(), Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 11/35] target/riscv: Convert RV64A insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 13/35] target/riscv: Convert RV64F insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 29/35] target/riscv: Remove gen_system(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 07/35] target/riscv: Convert RVXI fence insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 03/35] target/riscv: Convert RVXI branch insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 15/35] target/riscv: Convert RV64D insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2019/02/13
- [Qemu-riscv] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 14/35] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/02/20
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/02/21
[Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 02/11] RISC-V: Mark mstatus.fs dirty, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 01/11] RISC-V: Split out mstatus_fs from tb_flags, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 04/11] RISC-V: Use riscv prefix consistently on cpu helpers, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 05/11] RISC-V: Add priv_ver to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 11/11] riscv: Ensure the kernel start address is correctly cast, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 08/11] RISC-V: Add misa runtime write support, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 10/11] target/riscv: fix counter-enable checks in ctr(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 03/11] RISC-V: Implement mstatus.TSR/TW/TVM, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 06/11] RISC-V: Add misa to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 07/11] RISC-V: Add misa.MAFD checks to translate, Palmer Dabbelt, 2019/02/13
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1, Peter Maydell, 2019/02/14
Re: [Qemu-riscv] [PATCH v6 00/35] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/02/12
- Re: [Qemu-riscv] [PATCH v6 00/35] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/02/12
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree, Bastian Koppelmann, 2019/02/13
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/02/13
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/02/13
[Qemu-riscv] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support., Jim Wilson, 2019/02/12
- [Qemu-riscv] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files., Jim Wilson, 2019/02/12
- [Qemu-riscv] [PATCH v4 2/5] RISC-V: Add 64-bit gdb xml files., Jim Wilson, 2019/02/12
- [Qemu-riscv] [PATCH v4 3/5] RISC-V: Fixes to CSR_* register macros., Jim Wilson, 2019/02/12
- [Qemu-riscv] [PATCH v4 4/5] RISC-V: Add debug support for accessing CSRs., Jim Wilson, 2019/02/12
- [Qemu-riscv] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files., Jim Wilson, 2019/02/12
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files., Alistair Francis, 2019/02/12
[Qemu-riscv] [PATCH] SiFive RISC-V GPIO Device, Fabien Chouteau, 2019/02/12
- Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device, Alistair Francis, 2019/02/12
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device, Fabien Chouteau, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device, Peter Maydell, 2019/02/13
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device, Thomas Huth, 2019/02/13
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device, Palmer Dabbelt, 2019/02/13
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device, Peter Maydell, 2019/02/13
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device, Alistair Francis, 2019/02/13
[Qemu-riscv] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node, Lukas Auer, 2019/02/10
- Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node, Alistair Francis, 2019/02/11
[Qemu-riscv] [PATCH v1 00/11] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 01/11] riscv: Ensure the kernel start address is correctly cast, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 02/11] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 03/11] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 04/11] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 05/11] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 06/11] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 07/11] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 08/11] RISC-V: Change local interrupts from edge to level, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 09/11] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 10/11] RISC-V: Convert trap debugging to trace events, Alistair Francis, 2019/02/08
- [Qemu-riscv] [PATCH v1 11/11] RISC-V: Update load reservation comment in do_interrupt, Alistair Francis, 2019/02/08
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing, Alistair Francis, 2019/02/08
- Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing, Palmer Dabbelt, 2019/02/13
Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write, Alistair Francis, 2019/02/06
- Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write, Fabien Chouteau, 2019/02/07
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write, Alistair Francis, 2019/02/08
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write, Palmer Dabbelt, 2019/02/13
Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files., Alistair Francis, 2019/02/06
- Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files., Jim Wilson, 2019/02/06
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files., Richard Henderson, 2019/02/07
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files., Alistair Francis, 2019/02/08
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files., Jim Wilson, 2019/02/08
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files., Alistair Francis, 2019/02/08
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files., Palmer Dabbelt, 2019/02/11
Re: [Qemu-riscv] [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs., Alistair Francis, 2019/02/06
Re: [Qemu-riscv] [Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros., Alistair Francis, 2019/02/06
Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/5 v3] RISC-V: Add 64-bit gdb xml files., Alistair Francis, 2019/02/06
Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files., Alistair Francis, 2019/02/06
[Qemu-riscv] [PATCH v3 0/3] cutils: Cleanup, improve documentation, Philippe Mathieu-Daudé, 2019/02/04
- [Qemu-riscv] [PATCH v3 1/3] util/cutils: Move size_to_str() from "qemu-common.h" to "cutils.h", Philippe Mathieu-Daudé, 2019/02/04
- [Qemu-riscv] [PATCH v3 3/3] util/cutils: Move function documentations to the header, Philippe Mathieu-Daudé, 2019/02/04
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header, Markus Armbruster, 2019/02/05
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header, Peter Maydell, 2019/02/05
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header, Daniel P . Berrangé, 2019/02/05
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 3/3] util/cutils: Move function documentations to the header, Markus Armbruster, 2019/02/05
- [Qemu-riscv] [PATCH v3 2/3] util/cutils: Move ctype macros to "cutils.h", Philippe Mathieu-Daudé, 2019/02/04
  - Re: [Qemu-riscv] [PATCH v3 2/3] util/cutils: Move ctype macros to "cutils.h", Cornelia Huck, 2019/02/05
    - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 2/3] util/cutils: Move ctype macros to "cutils.h", Daniel P . Berrangé, 2019/02/05
[Qemu-riscv] [PULL] RISC-V Patches for 3.2, Part 3, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 07/10] RISC-V: Add misa.MAFD checks to translate, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 08/10] RISC-V: Add misa runtime write support, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 06/10] RISC-V: Add misa to DisasContext, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 05/10] RISC-V: Add priv_ver to DisasContext, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 10/10] target/riscv: fix counter-enable checks in ctr(), Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 03/10] RISC-V: Implement mstatus.TSR/TW/TVM, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 04/10] RISC-V: Use riscv prefix consistently on cpu helpers, Palmer Dabbelt, 2019/02/02
- [Qemu-riscv] [PULL 02/10] RISC-V: Mark mstatus.fs dirty, Palmer Dabbelt, 2019/02/02
Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3, Palmer Dabbelt, 2019/02/02
- Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3, Thomas Huth, 2019/02/04
  - Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3, Peter Maydell, 2019/02/04
    - Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3, Palmer Dabbelt, 2019/02/06
- Re: [Qemu-riscv] [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3, Palmer Dabbelt, 2019/02/02
Re: [Qemu-riscv] [Qemu-devel] [Bug 1814343] [NEW] Initrd not loaded on riscv32, Philippe Mathieu-Daudé, 2019/02/01
- Re: [Qemu-riscv] [Qemu-devel] [Bug 1814343] [NEW] Initrd not loaded on riscv32, Alistair Francis, 2019/02/05
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, no-reply, 2019/02/01

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