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Re: [Qemu-riscv] [PATCH v3 05/35] target/riscv: Convert RV64I load/store
From: |
Richard Henderson |
Subject: |
Re: [Qemu-riscv] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree |
Date: |
Wed, 31 Oct 2018 17:14:08 +0000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/31/18 1:19 PM, Bastian Koppelmann wrote:
> this splits the 64-bit only instructions into its own decode file such
> that we generate the decoder for these instructions only for the RISC-V
> 64 bit target.
>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> Signed-off-by: Peer Adelt <address@hidden>
> ---
> target/riscv/Makefile.objs | 8 +++++---
> target/riscv/insn64.decode | 25 +++++++++++++++++++++++++
> target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++
> target/riscv/translate.c | 7 -------
> 4 files changed, 50 insertions(+), 10 deletions(-)
> create mode 100644 target/riscv/insn64.decode
I did suggest using insn32-64.decode, so that insn64.decode is available for an
actual 64-bit instruction word, which is mentioned in the "Extensions" section
of the ISA manual.
However,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-riscv] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, (continued)
- [Qemu-riscv] [PATCH v3 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 07/35] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 15/35] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2018/10/31