[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 26/72] target/ppc: larx/stcx generation need only apply DEF_MEMOP(
From: |
Nicholas Piggin |
Subject: |
[PULL 26/72] target/ppc: larx/stcx generation need only apply DEF_MEMOP() once |
Date: |
Fri, 24 May 2024 09:06:59 +1000 |
Use DEF_MEMOP() consistently in larx and stcx. generation, and apply it
once when it's used rather than where the macros are expanded, to reduce
typing.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/translate.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 546f1754de..6c103dafe0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2849,7 +2849,7 @@ static void gen_load_locked(DisasContext *ctx, MemOp
memop)
gen_set_access_type(ctx, ACCESS_RES);
gen_addr_reg_index(ctx, t0);
- tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
+ tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN);
tcg_gen_mov_tl(cpu_reserve, t0);
tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
tcg_gen_mov_tl(cpu_reserve_val, gpr);
@@ -2862,9 +2862,9 @@ static void gen_##name(DisasContext *ctx) \
}
/* lwarx */
-LARX(lbarx, DEF_MEMOP(MO_UB))
-LARX(lharx, DEF_MEMOP(MO_UW))
-LARX(lwarx, DEF_MEMOP(MO_UL))
+LARX(lbarx, MO_UB)
+LARX(lharx, MO_UW)
+LARX(lwarx, MO_UL)
static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
TCGv EA, TCGCond cond, int addend)
@@ -3109,15 +3109,15 @@ static void gen_##name(DisasContext *ctx) \
gen_conditional_store(ctx, memop); \
}
-STCX(stbcx_, DEF_MEMOP(MO_UB))
-STCX(sthcx_, DEF_MEMOP(MO_UW))
-STCX(stwcx_, DEF_MEMOP(MO_UL))
+STCX(stbcx_, MO_UB)
+STCX(sthcx_, MO_UW)
+STCX(stwcx_, MO_UL)
#if defined(TARGET_PPC64)
/* ldarx */
-LARX(ldarx, DEF_MEMOP(MO_UQ))
+LARX(ldarx, MO_UQ)
/* stdcx. */
-STCX(stdcx_, DEF_MEMOP(MO_UQ))
+STCX(stdcx_, MO_UQ)
/* lqarx */
static void gen_lqarx(DisasContext *ctx)
--
2.43.0
- [PULL 14/72] target/ppc: Move neg, darn, mod{sw, uw} to decodetree., (continued)
- [PULL 14/72] target/ppc: Move neg, darn, mod{sw, uw} to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 13/72] target/ppc: Move divw[u, e, eu] instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 15/72] target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 16/72] target/ppc: Move div/mod fixed-point insns (64 bits operands) to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 18/72] target/ppc: Move logical fixed-point instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 17/72] target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 20/72] target/ppc: Move VMX integer logical instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 21/72] target/ppc: Move VMX integer max/min instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 19/72] target/ppc: Move VMX storage access instructions to decodetree, Nicholas Piggin, 2024/05/23
- [PULL 24/72] Add support for the clrbhrb and mfbhrbe instructions., Nicholas Piggin, 2024/05/23
- [PULL 26/72] target/ppc: larx/stcx generation need only apply DEF_MEMOP() once,
Nicholas Piggin <=
- [PULL 22/72] This commit is preparatory to the addition of Branch History Rolling Buffer (BHRB) functionality, which is being provided today starting with the P8 processor., Nicholas Piggin, 2024/05/23
- [PULL 28/72] target/ppc: Make checkstop actually stop the system, Nicholas Piggin, 2024/05/23
- [PULL 23/72] This commit continues adding support for the Branch History Rolling Buffer (BHRB) as is provided starting with the P8 processor and continuing with its successors. This commit is limited to the recording and filtering of taken branches., Nicholas Piggin, 2024/05/23
- [PULL 29/72] target/ppc: improve checkstop logging, Nicholas Piggin, 2024/05/23
- [PULL 27/72] target/ppc: Remove redundant MEMOP_GET_SIZE macro, Nicholas Piggin, 2024/05/23
- [PULL 32/72] target/ppc: Add PPR32 SPR, Nicholas Piggin, 2024/05/23
- [PULL 33/72] target/ppc: add helper to write per-LPAR SPRs, Nicholas Piggin, 2024/05/23
- [PULL 30/72] target/ppc: Implement attn instruction on BookS 64-bit processors, Nicholas Piggin, 2024/05/23
- [PULL 35/72] target/ppc: Add SMT support to PTCR SPR, Nicholas Piggin, 2024/05/23
- [PULL 34/72] target/ppc: Add SMT support to simple SPRs, Nicholas Piggin, 2024/05/23