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Re: [PATCH v3 4/5] hw/ppc: SPI controller wiring to P10 chip
From: |
Miles Glenn |
Subject: |
Re: [PATCH v3 4/5] hw/ppc: SPI controller wiring to P10 chip |
Date: |
Fri, 17 May 2024 14:26:34 -0500 |
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
-Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
> In this commit, create SPI controller on p10 chip and connect cs irq.
>
> The QOM tree of spi controller and seeprom are.
> /machine (powernv10-machine)
> /chip[0] (power10_v2.0-pnv-chip)
> /pib_spic[2] (pnv-spi-controller)
> /pnv-spi-bus.2 (SSI)
> /xscom-spi-controller-regs[0] (memory-region)
>
> /machine (powernv10-machine)
> /peripheral-anon (container)
> /device[0] (25csm04)
> /WP#[0] (irq)
> /ssi-gpio-cs[0] (irq)
>
> (qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
> "/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
>
> Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>
> ---
> include/hw/ppc/pnv_chip.h | 3 +++
> hw/ppc/pnv.c | 21 ++++++++++++++++++++-
> hw/ppc/pnv_spi_controller.c | 8 ++++++++
> 3 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
> index 8589f3291e..d464858f79 100644
> --- a/include/hw/ppc/pnv_chip.h
> +++ b/include/hw/ppc/pnv_chip.h
> @@ -6,6 +6,7 @@
> #include "hw/ppc/pnv_core.h"
> #include "hw/ppc/pnv_homer.h"
> #include "hw/ppc/pnv_n1_chiplet.h"
> +#include "hw/ssi/pnv_spi.h"
> #include "hw/ppc/pnv_lpc.h"
> #include "hw/ppc/pnv_occ.h"
> #include "hw/ppc/pnv_psi.h"
> @@ -118,6 +119,8 @@ struct Pnv10Chip {
> PnvSBE sbe;
> PnvHomer homer;
> PnvN1Chiplet n1_chiplet;
> +#define PNV10_CHIP_MAX_PIB_SPIC 6
> + PnvSpiController pib_spic[PNV10_CHIP_MAX_PIB_SPIC];
>
> uint32_t nr_quads;
> PnvQuad *quads;
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 6e3a5ccdec..6850592a85 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1829,6 +1829,11 @@ static void
> pnv_chip_power10_instance_init(Object *obj)
> for (i = 0; i < pcc->i2c_num_engines; i++) {
> object_initialize_child(obj, "i2c[*]", &chip10->i2c[i],
> TYPE_PNV_I2C);
> }
> +
> + for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC ; i++) {
> + object_initialize_child(obj, "pib_spic[*]", &chip10-
> >pib_spic[i],
> + TYPE_PNV_SPI_CONTROLLER);
> + }
> }
>
> static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error
> **errp)
> @@ -2043,7 +2048,21 @@ static void
> pnv_chip_power10_realize(DeviceState *dev, Error **errp)
> qdev_get_gpio_in(DEVICE(&chip10->psi),
> PSIHB9_IRQ_SBE_I2C));
> }
> -
> + /* PIB SPI Controller */
> + for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) {
> + object_property_set_int(OBJECT(&chip10->pib_spic[i]),
> "spic_num",
> + i, &error_fatal);
> + /* pib_spic[2] connected to 25csm04 which implements 1 byte
> transfer */
> + object_property_set_int(OBJECT(&chip10->pib_spic[i]),
> "transfer_len",
> + (i == 2) ? 1 : 4, &error_fatal);
> + if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT
> + (&chip10->pib_spic[i])),
> errp)) {
> + return;
> + }
> + pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE +
> + i * PNV10_XSCOM_PIB_SPIC_SIZE,
> + &chip10-
> >pib_spic[i].xscom_spic_regs);
> + }
> }
>
> static void pnv_rainier_i2c_init(PnvMachineState *pnv)
> diff --git a/hw/ppc/pnv_spi_controller.c
> b/hw/ppc/pnv_spi_controller.c
> index e87f583074..3d47e932de 100644
> --- a/hw/ppc/pnv_spi_controller.c
> +++ b/hw/ppc/pnv_spi_controller.c
> @@ -1067,9 +1067,17 @@ static void
> operation_sequencer(PnvSpiController *s)
> static void do_reset(DeviceState *dev)
> {
> PnvSpiController *s = PNV_SPICONTROLLER(dev);
> + DeviceState *ssi_dev;
>
> trace_pnv_spi_reset();
>
> + /* Connect cs irq */
> + ssi_dev = ssi_get_cs(s->ssi_bus, 0);
> + if (ssi_dev) {
> + qemu_irq cs_line = qdev_get_gpio_in_named(ssi_dev,
> SSI_GPIO_CS, 0);
> + qdev_connect_gpio_out_named(DEVICE(s), "cs", 0, cs_line);
> + }
> +
> /* Reset all N1 and N2 counters, and other constants */
> s->N2_bits = 0;
> s->N2_bytes = 0;
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