[PATCH v3 0/5] hw/ppc: SPI model

[Chalapathi V]

Hello,

Thank You so much for reviewing patch v2.
In patch v3, most of Cedric's comments are addressed.
- PnvSPIBus model is removed and added SSIBus to PnvSpiController.
- Added trace-events and removed SPI_DEBUG macro.
- Added Microchip's 25csm04 device on top of m25p80 and create seeprom
  device from a command line.
- Use qdev_connect_gpio_out_named instead of sysbus_connect_irq to
  connect cs.

The new qom-tree looks like below.
(qemu) info qom-tree 
/machine (powernv10-machine)
  /chip[0] (power10_v2.0-pnv-chip)
    /pib_spic[0] (pnv-spi-controller)
      /pnv-spi-bus.0 (SSI)
      /xscom-spi-controller-regs[0] (memory-region)
    /pib_spic[1] (pnv-spi-controller)
      /pnv-spi-bus.1 (SSI)
      /xscom-spi-controller-regs[0] (memory-region)
    /pib_spic[2] (pnv-spi-controller)
      /pnv-spi-bus.2 (SSI)
      /xscom-spi-controller-regs[0] (memory-region)
    /pib_spic[3] (pnv-spi-controller)
      /pnv-spi-bus.3 (SSI)
      /xscom-spi-controller-regs[0] (memory-region)
    /pib_spic[4] (pnv-spi-controller)
      /pnv-spi-bus.4 (SSI)
      /xscom-spi-controller-regs[0] (memory-region)
    /pib_spic[5] (pnv-spi-controller)
      /pnv-spi-bus.5 (SSI)
      /xscom-spi-controller-regs[0] (memory-region)

(qemu) info qom-tree 
/machine (powernv10-machine)
  /peripheral-anon (container)
    /device[0] (25csm04)
      /WP#[0] (irq)
      /ssi-gpio-cs[0] (irq)

Patches overview in v3.
PATCH1: Create a SPI controller model and implement configuration unit
        to model SCOM registers. Move header files to include/hw/ssi/
PATCH2: SPI controller model: implement sequencer FSM and shift engine.
PATCH3: Add Microchip's SEEPROM 25csm04 model on top of m25p80.
PATCH4: Connect SPI controllers to p10 chip and connect cs lines.
PATCH5: Write a qtest pnv-spi-seeprom-test to check the SPI transactions
        between spi controller and seeprom device.

Test covered:
Ran make check.

Thank You,
Chalapathi

Chalapathi V (5):
  ppc/pnv: Add SPI controller model
  ppc/pnv: Extend SPI model
  hw/block: Add Microchip's 25CSM04 to m25p80
  hw/ppc: SPI controller wiring to P10 chip
  tests/qtest: Add pnv-spi-seeprom qtest

 include/hw/ppc/pnv_chip.h          |    3 +
 include/hw/ppc/pnv_xscom.h         |    3 +
 include/hw/ssi/pnv_spi.h           |   72 ++
 include/hw/ssi/pnv_spi_regs.h      |  114 +++
 hw/block/m25p80.c                  |    3 +
 hw/ppc/pnv.c                       |   21 +-
 hw/ppc/pnv_spi_controller.c        | 1310 ++++++++++++++++++++++++++++
 tests/qtest/pnv-spi-seeprom-test.c |  129 +++
 hw/ppc/Kconfig                     |    2 +
 hw/ppc/meson.build                 |    1 +
 hw/ppc/trace-events                |   21 +
 tests/qtest/meson.build            |    1 +
 12 files changed, 1679 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/ssi/pnv_spi.h
 create mode 100644 include/hw/ssi/pnv_spi_regs.h
 create mode 100644 hw/ppc/pnv_spi_controller.c
 create mode 100644 tests/qtest/pnv-spi-seeprom-test.c

-- 
2.39.3