RE: [PATCH v3 11/29] target/hexagon: Prefer fast cpu_env() over slower CPU QOM cast macro

[Brian Cain]

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Sent: Monday, January 29, 2024 10:45 AM
> To: qemu-devel@nongnu.org
> Cc: qemu-riscv@nongnu.org; qemu-s390x@nongnu.org; Paolo Bonzini
> <pbonzini@redhat.com>; kvm@vger.kernel.org; qemu-ppc@nongnu.org;
> qemu-arm@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> Philippe Mathieu-Daudé <philmd@linaro.org>; Brian Cain
> <bcain@quicinc.com>
> Subject: [PATCH v3 11/29] target/hexagon: Prefer fast cpu_env() over slower
> CPU QOM cast macro
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
> 
> Mechanical patch produced running the command documented
> in scripts/coccinelle/cpu_env.cocci_template header.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/hexagon/cpu.c     | 25 ++++++-------------------
>  target/hexagon/gdbstub.c |  6 ++----
>  2 files changed, 8 insertions(+), 23 deletions(-)
> 
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index 085d6c0115..17a22aa7a5 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -236,10 +236,7 @@ static void hexagon_dump(CPUHexagonState *env,
> FILE *f, int flags)
> 
>  static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
>  {
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
> -    CPUHexagonState *env = &cpu->env;
> -
> -    hexagon_dump(env, f, flags);
> +    hexagon_dump(cpu_env(cs), f, flags);
>  }
> 
>  void hexagon_debug(CPUHexagonState *env)
> @@ -249,25 +246,19 @@ void hexagon_debug(CPUHexagonState *env)
> 
>  static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
>  {
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
> -    CPUHexagonState *env = &cpu->env;
> -    env->gpr[HEX_REG_PC] = value;
> +    cpu_env(cs)->gpr[HEX_REG_PC] = value;
>  }
> 
>  static vaddr hexagon_cpu_get_pc(CPUState *cs)
>  {
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
> -    CPUHexagonState *env = &cpu->env;
> -    return env->gpr[HEX_REG_PC];
> +    return cpu_env(cs)->gpr[HEX_REG_PC];
>  }
> 
>  static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
>                                              const TranslationBlock *tb)
>  {
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
> -    CPUHexagonState *env = &cpu->env;
>      tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> -    env->gpr[HEX_REG_PC] = tb->pc;
> +    cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;
>  }
> 
>  static bool hexagon_cpu_has_work(CPUState *cs)
> @@ -279,18 +270,14 @@ static void hexagon_restore_state_to_opc(CPUState
> *cs,
>                                           const TranslationBlock *tb,
>                                           const uint64_t *data)
>  {
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
> -    CPUHexagonState *env = &cpu->env;
> -
> -    env->gpr[HEX_REG_PC] = data[0];
> +    cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
>  }
> 
>  static void hexagon_cpu_reset_hold(Object *obj)
>  {
>      CPUState *cs = CPU(obj);
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
>      HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);
> -    CPUHexagonState *env = &cpu->env;
> +    CPUHexagonState *env = cpu_env(cs);
> 
>      if (mcc->parent_phases.hold) {
>          mcc->parent_phases.hold(obj);
> diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
> index 54d37e006e..f773f8ea4f 100644
> --- a/target/hexagon/gdbstub.c
> +++ b/target/hexagon/gdbstub.c
> @@ -22,8 +22,7 @@
> 
>  int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
>  {
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
> -    CPUHexagonState *env = &cpu->env;
> +    CPUHexagonState *env = cpu_env(cs);
> 
>      if (n == HEX_REG_P3_0_ALIASED) {
>          uint32_t p3_0 = 0;
> @@ -42,8 +41,7 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray
> *mem_buf, int n)
> 
>  int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
>  {
> -    HexagonCPU *cpu = HEXAGON_CPU(cs);
> -    CPUHexagonState *env = &cpu->env;
> +    CPUHexagonState *env = cpu_env(cs);
> 
>      if (n == HEX_REG_P3_0_ALIASED) {
>          uint32_t p3_0 = ldtul_p(mem_buf);
> --
> 2.41.0

Reviewed-by: Brian Cain <bcain@quicinc.com>