Re: [PATCH] util: optimise flush_idcache_range when the ppc host has coherent icache

[Richard Henderson]

On 5/19/22 17:04, Nicholas Piggin wrote:
> > I'm even more tempted to merge the two files to put all of the machine-specific 
> > cache data
> > in the same place, then this variable can be static.  There's even an existing 
> > TODO
> > comment in cacheflush.c for aarch64.
>
> That might be nice. Do you want me to look at doing that first?

If you wouldn't mind, please do.  I'll take care of aarch64 cleanup related to the TODO 
afterward.

> > >        b = rw & ~(dsize - 1);
> > > +
> > > +    if (have_coherent_icache) {
> > > +        asm volatile ("sync" : : : "memory");
> > > +        asm volatile ("icbi 0,%0" : : "r"(b) : "memory");
> > > +        asm volatile ("isync" : : : "memory");
> > > +        return;
> > > +    }
> >
> > Where can I find definitive rules on this?
>
> In processor manuals (I don't know if there are any notes about this in
> the ISA, I would be tempted to say there should be since many processors
> implement it).
>
> POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi)
>
> https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
...
> Yeah it's just a funny sequence the processor implements. It treats icbi
> almost as a no-op except that it sets a flag such that the next isync
> will flush and refetch the pipeline. It doesn't do any cache flushing.

Thanks.  A short comment in the code would be helpful here.

Also, since the docs say "any address", you might as well just use rx unmodified and sink 
the computation of 'b' back next to 'e'.


r~