[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 13/41] ppc/ppc405: Fix TLB flushing
From: |
Cédric Le Goater |
Subject: |
[PULL 13/41] ppc/ppc405: Fix TLB flushing |
Date: |
Mon, 31 Jan 2022 12:07:43 +0100 |
Commit cd0c6f473532 did not take into account 405 CPUs when adding
support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH
flag when the SPR_40x_PID is set or a TLB updated.
Cc: Thomas Huth <thuth@redhat.com>
Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220113180352.1234512-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/mmu_helper.c | 12 +++++++++++-
target/ppc/translate.c | 2 +-
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index d318837ea5cc..bdbbd5e1d90f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -707,6 +707,7 @@ DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_2(store_40x_pid, void, env, tl)
DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
DEF_HELPER_2(store_40x_sler, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 59df6952aea1..a2a52a12c3a4 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -664,6 +664,14 @@ static inline int booke_page_size_to_tlb(target_ulong
page_size)
#define PPC4XX_TLBLO_ATTR_MASK 0x000000FF
#define PPC4XX_TLBLO_RPN_MASK 0xFFFFFC00
+void helper_store_40x_pid(CPUPPCState *env, target_ulong val)
+{
+ if (env->spr[SPR_40x_PID] != val) {
+ env->spr[SPR_40x_PID] = val;
+ env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+ }
+}
+
target_ulong helper_4xx_tlbre_hi(CPUPPCState *env, target_ulong entry)
{
ppcemb_tlb_t *tlb;
@@ -681,7 +689,7 @@ target_ulong helper_4xx_tlbre_hi(CPUPPCState *env,
target_ulong entry)
size = PPC4XX_TLBHI_SIZE_DEFAULT;
}
ret |= size << PPC4XX_TLBHI_SIZE_SHIFT;
- env->spr[SPR_40x_PID] = tlb->PID;
+ helper_store_40x_pid(env, tlb->PID);
return ret;
}
@@ -794,6 +802,8 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong
entry,
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
+
+ env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
}
target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9d2adc0caee0..d61c6f0e8f91 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -894,7 +894,7 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int
gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF);
- gen_store_spr(SPR_40x_PID, t0);
+ gen_helper_store_40x_pid(cpu_env, t0);
tcg_temp_free(t0);
}
--
2.34.1
- [PULL 37/41] target/ppc: 74xx: Program exception cleanup, (continued)
- [PULL 37/41] target/ppc: 74xx: Program exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 17/41] target/ppc: Simplify powerpc_excp_40x, Cédric Le Goater, 2022/01/31
- [PULL 22/41] target/ppc: 405: Alignment exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 21/41] target/ppc: 405: System call exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 34/41] target/ppc: Simplify powerpc_excp_74xx, Cédric Le Goater, 2022/01/31
- [PULL 09/41] spapr.c: check bus != NULL in spapr_get_fw_dev_path(), Cédric Le Goater, 2022/01/31
- [PULL 04/41] ppc/pnv: Fail DMA access if page permissions are not correct, Cédric Le Goater, 2022/01/31
- [PULL 03/41] target/ppc/mmu_common: Fix SRR1/MSR error code on Book-E, Cédric Le Goater, 2022/01/31
- [PULL 08/41] target/ppc: fix 'skip KVM' cond in cpu_interrupt_exittb(), Cédric Le Goater, 2022/01/31
- [PULL 20/41] target/ppc: 405: External exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 13/41] ppc/ppc405: Fix TLB flushing,
Cédric Le Goater <=
- Re: [PULL 00/41] ppc queue, Peter Maydell, 2022/01/31