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[PULL 01/41] spapr: Force 32bit when resetting a core
From: |
Cédric Le Goater |
Subject: |
[PULL 01/41] spapr: Force 32bit when resetting a core |
Date: |
Mon, 31 Jan 2022 12:07:31 +0100 |
From: Alexey Kardashevskiy <aik@ozlabs.ru>
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As nothing enforces LE anywhere, this drops it for VOF.
The goal is to make VOF work with TCG as otherwise it barfs with
qemu: fatal: TCG hflags mismatch (current:0x6c000004 rebuilt:0x6c000000)
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220107072423.2278113-1-aik@ozlabs.ru>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_cpu_core.c | 5 +++++
hw/ppc/spapr_vof.c | 2 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index a57ba70a8781..a781e97f8d1d 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -37,6 +37,11 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
cpu_reset(cs);
+ /*
+ * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
+ * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
+ */
+ env->msr &= ~(1ULL << MSR_SF);
env->spr[SPR_HIOR] = 0;
lpcr = env->spr[SPR_LPCR];
diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c
index 40ce8fe0037c..a33f940c32bb 100644
--- a/hw/ppc/spapr_vof.c
+++ b/hw/ppc/spapr_vof.c
@@ -88,8 +88,6 @@ void spapr_vof_reset(SpaprMachineState *spapr, void *fdt,
Error **errp)
spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT,
stack_ptr, spapr->initrd_base,
spapr->initrd_size);
- /* VOF is 32bit BE so enforce MSR here */
- first_ppc_cpu->env.msr &= ~((1ULL << MSR_SF) | (1ULL << MSR_LE));
/*
* At this point the expected allocation map is:
--
2.34.1
- [PULL 11/41] target/ppc: Put do_rfi under a TCG-only block, (continued)
- [PULL 11/41] target/ppc: Put do_rfi under a TCG-only block, Cédric Le Goater, 2022/01/31
- [PULL 14/41] target/ppc: 405: Rename MSR_POW to MSR_WE, Cédric Le Goater, 2022/01/31
- [PULL 25/41] target/ppc: 405: Instruction storage interrupt cleanup, Cédric Le Goater, 2022/01/31
- [PULL 33/41] target/ppc: Introduce powerpc_excp_74xx, Cédric Le Goater, 2022/01/31
- [PULL 06/41] ppc/pnv: use a do-while() loop in pnv_phb4_translate_tve(), Cédric Le Goater, 2022/01/31
- [PULL 19/41] target/ppc: 405: Machine check exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 10/41] target/ppc: Fix test on mmu_model in hreg_compute_hflags_value(), Cédric Le Goater, 2022/01/31
- [PULL 27/41] target/ppc: 405: Watchdog timer exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 35/41] target/ppc: 74xx: Machine Check exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 32/41] target/ppc: books: Program exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 01/41] spapr: Force 32bit when resetting a core,
Cédric Le Goater <=
- [PULL 30/41] target/ppc: books: Machine Check exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 05/41] ppc/pnv: use a do-while() loop in pnv_phb3_translate_tve(), Cédric Le Goater, 2022/01/31
- [PULL 16/41] target/ppc: Introduce powerpc_excp_40x, Cédric Le Goater, 2022/01/31
- [PULL 12/41] hw/ppc/vof: Add missing includes, Cédric Le Goater, 2022/01/31
- [PULL 38/41] target/ppc: 74xx: System Call exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 29/41] target/ppc: Simplify powerpc_excp_books, Cédric Le Goater, 2022/01/31
- [PULL 41/41] target/ppc: Remove support for the PowerPC 602 CPU, Cédric Le Goater, 2022/01/31
- [PULL 24/41] target/ppc: 405: Data Storage exception cleanup, Cédric Le Goater, 2022/01/31
- [PULL 40/41] target/ppc: 74xx: Set SRRs directly in exception code, Cédric Le Goater, 2022/01/31
- [PULL 07/41] ppc/xive: check return value of ldq_be_dma(), Cédric Le Goater, 2022/01/31