Re: [PATCH] target/ppc: Add extra float instructions to POWER5P processors

[Cédric Le Goater]

On 1/10/22 17:19, Cédric Le Goater wrote:
> ISA v2.03 introduced Floating Round to Integer instructions : frin,
> friz, frip, and frim. Add them to POWER5+.
>
> The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
> Estimate) instruction which was introduced in ISA v2.0x. The
> architecture document says its optional and that might the reason why
> it has been kept under the PPC_FLOAT_EXT. This means 970 CPUs can not
> use it under QEMU.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>


Applied to ppc7.0.

Thanks,

C.