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[PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only
From: |
David Gibson |
Subject: |
[PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only |
Date: |
Fri, 27 Aug 2021 17:09:36 +1000 |
From: Cédric Le Goater <clg@kaod.org>
There is no need to keep the DD1 chip model as it will never be
publicly available.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-3-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c | 2 +-
include/hw/ppc/pnv.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d16dd2d080..b122251d1a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1916,7 +1916,7 @@ static void pnv_machine_power10_class_init(ObjectClass
*oc, void *data)
static const char compat[] = "qemu,powernv10\0ibm,powernv";
mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
- mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 8c2a15a0fb..4de8414df2 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -347,7 +347,7 @@ static const TypeInfo pnv_core_infos[] = {
DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
- DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"),
+ DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"),
};
DEFINE_TYPES(pnv_core_infos)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index d69cee17b2..3fec7c87d8 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -170,7 +170,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
TYPE_PNV_CHIP_POWER9)
-#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
+#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
--
2.31.1
- [PULL 00/18] ppc-for-6.2 queue 20210827, David Gibson, 2021/08/27
- [PULL 02/18] spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree, David Gibson, 2021/08/27
- [PULL 01/18] xive: Remove extra '0x' prefix in trace events, David Gibson, 2021/08/27
- [PULL 04/18] target/ppc: moved ppc_store_sdr1 to mmu_common.c, David Gibson, 2021/08/27
- [PULL 03/18] target/ppc: divided mmu_helper.c in 2 files, David Gibson, 2021/08/27
- [PULL 05/18] target/ppc: moved store_40x_sler to helper_regs.c, David Gibson, 2021/08/27
- [PULL 09/18] ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode, David Gibson, 2021/08/27
- [PULL 07/18] ppc: Add a POWER10 DD2 CPU, David Gibson, 2021/08/27
- [PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only,
David Gibson <=
- [PULL 10/18] ppc/pnv: Use a simple incrementing index for the chip-id, David Gibson, 2021/08/27
- [PULL 13/18] ppc/xive: Export PQ get/set routines, David Gibson, 2021/08/27
- [PULL 12/18] ppc/pnv: add a chip topology index for POWER10, David Gibson, 2021/08/27
- [PULL 11/18] ppc/pnv: Distribute RAM among the chips, David Gibson, 2021/08/27
- [PULL 06/18] ppc/pnv: update skiboot to commit 820d43c0a775., David Gibson, 2021/08/27
- [PULL 17/18] include/qemu/int128.h: introduce bswap128s, David Gibson, 2021/08/27
- [PULL 14/18] ppc/xive: Export xive_presenter_notify(), David Gibson, 2021/08/27
- [PULL 15/18] include/qemu/int128.h: define struct Int128 according to the host endianness, David Gibson, 2021/08/27
- [PULL 16/18] target/ppc: fix vextu[bhw][lr]x helpers, David Gibson, 2021/08/27
- [PULL 18/18] target/ppc: fix vector registers access in gdbstub for little-endian, David Gibson, 2021/08/27