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Re: [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10
From: |
David Gibson |
Subject: |
Re: [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10 |
Date: |
Wed, 25 Aug 2021 16:06:48 +1000 |
On Mon, Aug 09, 2021 at 03:45:33PM +0200, Cédric Le Goater wrote:
> Our OCC model is very mininal and POWER10 can simply reuse the OCC
> model we introduced for POWER9.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> include/hw/ppc/pnv.h | 1 +
> include/hw/ppc/pnv_occ.h | 2 ++
> include/hw/ppc/pnv_xscom.h | 3 +++
> hw/ppc/pnv.c | 10 ++++++++++
> hw/ppc/pnv_occ.c | 16 ++++++++++++++++
> 5 files changed, 32 insertions(+)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index b773b09f9f8e..a299fbc7f25c 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -127,6 +127,7 @@ struct Pnv10Chip {
> PnvXive2 xive;
> Pnv9Psi psi;
> PnvLpcController lpc;
> + PnvOCC occ;
> };
>
> #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
> diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> index b78185aecaf2..f982ba002481 100644
> --- a/include/hw/ppc/pnv_occ.h
> +++ b/include/hw/ppc/pnv_occ.h
> @@ -32,6 +32,8 @@ DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
> #define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
> DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
> TYPE_PNV9_OCC)
> +#define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
> +DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
>
> #define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
> #define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index 188da874a4b0..151df15378d1 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -131,6 +131,9 @@ struct PnvXScomInterfaceClass {
> #define PNV10_XSCOM_PSIHB_BASE 0x3011D00
> #define PNV10_XSCOM_PSIHB_SIZE 0x100
>
> +#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
> +#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
> +
> #define PNV10_XSCOM_XIVE2_BASE 0x2010800
> #define PNV10_XSCOM_XIVE2_SIZE 0x400
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 28c928b3985a..f75d90e61fa8 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1602,6 +1602,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
> "xive-fabric");
> object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
> object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
> + object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
> }
>
> static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
> @@ -1667,6 +1668,15 @@ static void pnv_chip_power10_realize(DeviceState *dev,
> Error **errp)
> chip->fw_mr = &chip10->lpc.isa_fw;
> chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
> (uint64_t)
> PNV10_LPCM_BASE(chip));
> +
> + /* Create the simplified OCC model */
> + object_property_set_link(OBJECT(&chip10->occ), "psi",
> OBJECT(&chip10->psi),
> + &error_abort);
> + if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
> + return;
> + }
> + pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
> + &chip10->occ.xscom_regs);
> }
>
> static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> index 5a716c256edc..4ed66f5e1fcc 100644
> --- a/hw/ppc/pnv_occ.c
> +++ b/hw/ppc/pnv_occ.c
> @@ -236,7 +236,9 @@ static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
> static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
> {
> PnvOCCClass *poc = PNV_OCC_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
>
> + dc->desc = "PowerNV OCC Controller (POWER9)";
> poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
> poc->xscom_ops = &pnv_occ_power9_xscom_ops;
> poc->psi_irq = PSIHB9_IRQ_OCC;
> @@ -249,6 +251,19 @@ static const TypeInfo pnv_occ_power9_type_info = {
> .class_init = pnv_occ_power9_class_init,
> };
>
> +static void pnv_occ_power10_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV OCC Controller (POWER10)";
> +}
> +
> +static const TypeInfo pnv_occ_power10_type_info = {
> + .name = TYPE_PNV10_OCC,
> + .parent = TYPE_PNV9_OCC,
> + .class_init = pnv_occ_power10_class_init,
> +};
> +
> static void pnv_occ_realize(DeviceState *dev, Error **errp)
> {
> PnvOCC *occ = PNV_OCC(dev);
> @@ -297,6 +312,7 @@ static void pnv_occ_register_types(void)
> type_register_static(&pnv_occ_type_info);
> type_register_static(&pnv_occ_power8_type_info);
> type_register_static(&pnv_occ_power9_type_info);
> + type_register_static(&pnv_occ_power10_type_info);
> }
>
> type_init(pnv_occ_register_types);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [PATCH 09/26] ppc/xive2: Introduce a XIVE2 core framework, (continued)
- [PATCH 14/26] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge, Cédric Le Goater, 2021/08/09
- [PATCH 15/26] ppc/pnv: Add a HOMER model to POWER10, Cédric Le Goater, 2021/08/09
- [PATCH 16/26] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10), Cédric Le Goater, 2021/08/09
- [PATCH 22/26] ppc/pnv: add XIVE Gen2 TIMA support, Cédric Le Goater, 2021/08/09
- [PATCH 11/26] ppc/pnv: Add a XIVE2 controller to the POWER10 chip., Cédric Le Goater, 2021/08/09
- [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10, Cédric Le Goater, 2021/08/09
- Re: [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10,
David Gibson <=
- [PATCH 18/26] ppc/xive: Add support for PQ state bits offload, Cédric Le Goater, 2021/08/09
- [PATCH 10/26] ppc/xive2: Introduce a presenter matching routine, Cédric Le Goater, 2021/08/09
- [PATCH 19/26] ppc/pnv: Add support for PQ offload on PHB5, Cédric Le Goater, 2021/08/09
- [PATCH 21/26] pnv/xive2: Introduce new capability bits, Cédric Le Goater, 2021/08/09
- [PATCH 17/26] ppc/xive2: Add support for notification injection on ESB pages, Cédric Le Goater, 2021/08/09
- [PATCH 23/26] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1), Cédric Le Goater, 2021/08/09
- [PATCH 26/26] pnv/xive2: Add support for 8bits thread id, Cédric Le Goater, 2021/08/09
- [PATCH 24/26] xive2: Add a get_config() handler for the router configuration, Cédric Le Goater, 2021/08/09