Re: [PATCH 2/2] i2c/smbus_eeprom: Add feature bit to SPD data

[Corey Minyard]

On Thu, Jul 15, 2021 at 06:50:44PM +0200, BALATON Zoltan wrote:
> Add the differential clock input feature bit to the generated SPD
> data. Most guests don't seem to care but pegasos2 firmware version 1.2
> checks for this bit and stops with unsupported module type error if
> it's not present. Since this feature is likely present on real memory
> modules add it in the general code rather than patching the generated
> SPD data in pegasos2 board only.
> 
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>

I checked this all out and it looks correct to me.  I can take it in my
tree, if necessary.  Feature freeze is in two days, so probably not for
6.1, though it could be pushed into there if its needed in 6.1.

Or:

Acked-by: Corey Minyard <cminyard@mvista.com>

if someone else wants to take it.  This particular code really doesn't
belong in eeprom.c, I don't think, but I'm not sure where else to put
it.  And I can look in the SPD tables as well as anyone :).

corey

> ---
> I've tested it with the firmware of pegasos2, sam460ex, fuloong2e and
> g3beige (latter is not upstream yet) that are the only ones using this
> function currently. Probably this could go in via PPC tree with my
> other pegasos2 fix if respective maitainers ack this patch.
> 
>  hw/i2c/smbus_eeprom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
> index 4d2bf99207..12c5741f38 100644
> --- a/hw/i2c/smbus_eeprom.c
> +++ b/hw/i2c/smbus_eeprom.c
> @@ -276,7 +276,7 @@ uint8_t *spd_data_generate(enum sdram_type type, 
> ram_addr_t ram_size)
>      spd[18] = 12;   /* ~CAS latencies supported */
>      spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported 
> */
>      spd[20] = 2;    /* DIMM type / ~WE latencies */
> -                    /* module features */
> +    spd[21] = (type < DDR2 ? 0x20 : 0); /* module features */
>                      /* memory chip features */
>      spd[23] = 0x12; /* clock cycle time @ medium CAS latency */
>                      /* data access time */
> -- 
> 2.21.4
>