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Re: [PATCH v4 01/31] target/ppc: Add cia field to DisasContext
From: |
David Gibson |
Subject: |
Re: [PATCH v4 01/31] target/ppc: Add cia field to DisasContext |
Date: |
Thu, 13 May 2021 14:03:17 +1000 |
On Wed, May 12, 2021 at 03:54:11PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate.c | 36 +++++++++++++++++++-----------------
> 1 file changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 98850f0c30..9abe03222d 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -154,6 +154,7 @@ void ppc_translate_init(void)
> /* internal defines */
> struct DisasContext {
> DisasContextBase base;
> + target_ulong cia; /* current instruction address */
> uint32_t opcode;
> uint32_t exception;
> /* Routine used to access memory */
> @@ -253,7 +254,7 @@ static void gen_exception_err(DisasContext *ctx, uint32_t
> excp, uint32_t error)
> * faulting instruction
> */
> if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->base.pc_next - 4);
> + gen_update_nip(ctx, ctx->cia);
> }
> t0 = tcg_const_i32(excp);
> t1 = tcg_const_i32(error);
> @@ -272,7 +273,7 @@ static void gen_exception(DisasContext *ctx, uint32_t
> excp)
> * faulting instruction
> */
> if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->base.pc_next - 4);
> + gen_update_nip(ctx, ctx->cia);
> }
> t0 = tcg_const_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> @@ -4140,7 +4141,7 @@ static void gen_eieio(DisasContext *ctx)
> */
> if (!(ctx->insns_flags2 & PPC2_ISA300)) {
> qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
> - TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
> + TARGET_FMT_lx "\n", ctx->cia);
> } else {
> bar = TCG_MO_ST_LD;
> }
> @@ -4809,14 +4810,14 @@ static void gen_b(DisasContext *ctx)
> li = LI(ctx->opcode);
> li = (li ^ 0x02000000) - 0x02000000;
> if (likely(AA(ctx->opcode) == 0)) {
> - target = ctx->base.pc_next + li - 4;
> + target = ctx->cia + li;
> } else {
> target = li;
> }
> if (LK(ctx->opcode)) {
> gen_setlr(ctx, ctx->base.pc_next);
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_goto_tb(ctx, 0, target);
> }
>
> @@ -4915,11 +4916,11 @@ static void gen_bcond(DisasContext *ctx, int type)
> }
> tcg_temp_free_i32(temp);
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> if (type == BCOND_IM) {
> target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
> if (likely(AA(ctx->opcode) == 0)) {
> - gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
> + gen_goto_tb(ctx, 0, ctx->cia + li);
> } else {
> gen_goto_tb(ctx, 0, li);
> }
> @@ -5035,7 +5036,7 @@ static void gen_rfi(DisasContext *ctx)
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfi(cpu_env);
> gen_sync_exception(ctx);
> #endif
> @@ -5052,7 +5053,7 @@ static void gen_rfid(DisasContext *ctx)
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfid(cpu_env);
> gen_sync_exception(ctx);
> #endif
> @@ -5069,7 +5070,7 @@ static void gen_rfscv(DisasContext *ctx)
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> }
> - gen_update_cfar(ctx, ctx->base.pc_next - 4);
> + gen_update_cfar(ctx, ctx->cia);
> gen_helper_rfscv(cpu_env);
> gen_sync_exception(ctx);
> #endif
> @@ -5112,7 +5113,7 @@ static void gen_scv(DisasContext *ctx)
>
> /* Set the PC back to the faulting instruction. */
> if (ctx->exception == POWERPC_EXCP_NONE) {
> - gen_update_nip(ctx, ctx->base.pc_next - 4);
> + gen_update_nip(ctx, ctx->cia);
> }
> gen_helper_scv(cpu_env, tcg_constant_i32(lev));
>
> @@ -5320,7 +5321,7 @@ static inline void gen_op_mfspr(DisasContext *ctx)
> if (sprn != SPR_PVR) {
> qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged
> spr "
> "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn,
> sprn,
> - ctx->base.pc_next - 4);
> + ctx->cia);
> }
> gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
> }
> @@ -5334,7 +5335,7 @@ static inline void gen_op_mfspr(DisasContext *ctx)
> /* Not defined */
> qemu_log_mask(LOG_GUEST_ERROR,
> "Trying to read invalid spr %d (0x%03x) at "
> - TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
> + TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
>
> /*
> * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
> @@ -5498,7 +5499,7 @@ static void gen_mtspr(DisasContext *ctx)
> /* Privilege exception */
> qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
> "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
> - ctx->base.pc_next - 4);
> + ctx->cia);
> gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
> }
> } else {
> @@ -5512,7 +5513,7 @@ static void gen_mtspr(DisasContext *ctx)
> /* Not defined */
> qemu_log_mask(LOG_GUEST_ERROR,
> "Trying to write invalid spr %d (0x%03x) at "
> - TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
> + TARGET_FMT_lx "\n", sprn, sprn, ctx->cia);
>
>
> /*
> @@ -9339,6 +9340,7 @@ static void ppc_tr_translate_insn(DisasContextBase
> *dcbase, CPUState *cs)
> LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
> ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
>
> + ctx->cia = ctx->base.pc_next;
> ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next,
> need_byteswap(ctx));
>
> @@ -9368,7 +9370,7 @@ static void ppc_tr_translate_insn(DisasContextBase
> *dcbase, CPUState *cs)
> TARGET_FMT_lx " %d\n",
> opc1(ctx->opcode), opc2(ctx->opcode),
> opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
> + ctx->opcode, ctx->cia, (int)msr_ir);
> } else {
> uint32_t inval;
>
> @@ -9385,7 +9387,7 @@ static void ppc_tr_translate_insn(DisasContextBase
> *dcbase, CPUState *cs)
> TARGET_FMT_lx "\n", ctx->opcode & inval,
> opc1(ctx->opcode), opc2(ctx->opcode),
> opc3(ctx->opcode), opc4(ctx->opcode),
> - ctx->opcode, ctx->base.pc_next - 4);
> + ctx->opcode, ctx->cia);
> gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> ctx->base.is_jmp = DISAS_NORETURN;
> return;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH v4 00/31] Base for adding PowerPC 64-bit instructions, matheus . ferst, 2021/05/12
- [PATCH v4 01/31] target/ppc: Add cia field to DisasContext, matheus . ferst, 2021/05/12
- Re: [PATCH v4 01/31] target/ppc: Add cia field to DisasContext,
David Gibson <=
- [PATCH v4 02/31] target/ppc: Split out decode_legacy, matheus . ferst, 2021/05/12
- [PATCH v4 03/31] target/ppc: Move DISAS_NORETURN setting into gen_exception*, matheus . ferst, 2021/05/12
- [PATCH v4 05/31] target/ppc: Remove special case for POWERPC_EXCP_TRAP, matheus . ferst, 2021/05/12
- [PATCH v4 04/31] target/ppc: Remove special case for POWERPC_SYSCALL, matheus . ferst, 2021/05/12
- [PATCH v4 06/31] target/ppc: Simplify gen_debug_exception, matheus . ferst, 2021/05/12