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[PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instru
From: |
matheus . ferst |
Subject: |
[PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions |
Date: |
Wed, 12 May 2021 15:54:38 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implements the following PowerISA v3.1 instructions:
setbc: Set Boolean Condition
setbcr: Set Boolean Condition Reverse
setnbc: Set Negative Boolean Condition
setnbcr: Set Negative Boolean Condition Reverse
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 10 ++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 21 +++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 8460100177..d69c0bc14c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -26,6 +26,9 @@
&X rt ra rb
@X ...... rt:5 ra:5 rb:5 .......... . &X
+&X_bi rt bi
+@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -83,3 +86,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+
+### Move To/From System Register Instructions
+
+SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
+SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
+SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
+SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 04a974214f..37dd25148c 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -201,3 +201,24 @@ static bool trans_PNOP(DisasContext *ctx, arg_PNOP *a)
}
return true;
}
+
+static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool
rev)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ uint32_t mask = 0x08 >> (a->bi & 0x03);
+ TCGv temp = tcg_temp_new();
+
+ tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]);
+ tcg_gen_andi_tl(temp, temp, mask);
+ tcg_gen_movcond_tl(a->r?TCG_COND_EQ:TCG_COND_NE, cpu_gpr[a->rt], temp,
+ tcg_constant_tl(0), tcg_constant_tl(a->n?-1:1),
+ tcg_constant_tl(0));
+ tcg_temp_free(temp);
+
+ return true;
+}
+
+TRANS(SETBC, do_set_bool_cond, false, false)
+TRANS(SETBCR, do_set_bool_cond, false, true)
+TRANS(SETNBC, do_set_bool_cond, true, false)
+TRANS(SETNBCR, do_set_bool_cond, true, true)
--
2.25.1
- [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, (continued)
- [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, matheus . ferst, 2021/05/12
- [PATCH v4 22/31] target/ppc: Implement PNOP, matheus . ferst, 2021/05/12
- [PATCH v4 23/31] TCG: add tcg_constant_tl, matheus . ferst, 2021/05/12
- [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree, matheus . ferst, 2021/05/12
- [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions, matheus . ferst, 2021/05/12
- [PATCH v4 26/31] target/ppc: Move D/DS/X-form integer stores to decodetree, matheus . ferst, 2021/05/12
- [PATCH v4 27/31] target/ppc: Implement prefixed integer store instructions, matheus . ferst, 2021/05/12
- [PATCH v4 28/31] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions,
matheus . ferst <=
- [PATCH v4 29/31] target/ppc: Implement cfuged instruction, matheus . ferst, 2021/05/12
- [PATCH v4 30/31] target/ppc: Implement vcfuged instruction, matheus . ferst, 2021/05/12
- [PATCH v4 31/31] target/ppc: Move addpcis to decodetree, matheus . ferst, 2021/05/12