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[PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions
From: |
matheus . ferst |
Subject: |
[PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions |
Date: |
Wed, 12 May 2021 15:54:28 -0300 |
From: Richard Henderson <richard.henderson@linaro.org>
These will be used by the decodetree trans_* functions
to early-exit when the instruction set is not enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index cd4b34aa91..153c61e8ec 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7753,6 +7753,32 @@ static inline void set_avr64(int regno, TCGv_i64 src,
bool high)
tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
}
+/*
+ * Helpers for trans_* functions to check for specific insns flags.
+ * Use token pasting to ensure that we use the proper flag with the
+ * proper variable.
+ */
+#define REQUIRE_INSNS_FLAGS(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags & PPC_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \
+ do { \
+ if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \
+ return false; \
+ } \
+ } while (0)
+
+/* Then special-case the check for 64-bit so that we elide code for ppc32. */
+#if TARGET_LONG_BITS == 32
+# define REQUIRE_64BIT(CTX) return false
+#else
+# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B)
+#endif
+
#include "translate/fp-impl.c.inc"
#include "translate/vmx-impl.c.inc"
--
2.25.1
- Re: [PATCH v4 10/31] target/ppc: Introduce gen_icount_io_start, (continued)
- [PATCH v4 11/31] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE, matheus . ferst, 2021/05/12
- [PATCH v4 12/31] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN, matheus . ferst, 2021/05/12
- [PATCH v4 13/31] target/ppc: Remove DisasContext.exception, matheus . ferst, 2021/05/12
- [PATCH v4 14/31] target/ppc: Move single-step check to ppc_tr_tb_stop, matheus . ferst, 2021/05/12
- [PATCH v4 15/31] target/ppc: Tidy exception vs exit_tb, matheus . ferst, 2021/05/12
- [PATCH v4 16/31] target/ppc: Mark helper_raise_exception* as noreturn, matheus . ferst, 2021/05/12
- [PATCH v4 17/31] target/ppc: Use translator_loop_temp_check, matheus . ferst, 2021/05/12
- [PATCH v4 18/31] target/ppc: Introduce macros to check isa extensions,
matheus . ferst <=
- [PATCH v4 19/31] target/ppc: Move page crossing check to ppc_tr_translate_insn, matheus . ferst, 2021/05/12
- [PATCH v4 20/31] target/ppc: Add infrastructure for prefixed insns, matheus . ferst, 2021/05/12
- [PATCH v4 21/31] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI, matheus . ferst, 2021/05/12
- [PATCH v4 22/31] target/ppc: Implement PNOP, matheus . ferst, 2021/05/12
- [PATCH v4 23/31] TCG: add tcg_constant_tl, matheus . ferst, 2021/05/12
- [PATCH v4 24/31] target/ppc: Move D/DS/X-form integer loads to decodetree, matheus . ferst, 2021/05/12
- [PATCH v4 25/31] target/ppc: Implement prefixed integer load instructions, matheus . ferst, 2021/05/12