[PATCH] target/ppc/spapr: Update H_GET_CPU_CHARACTERISTICS bits

[Nicholas Piggin]

There are several new bits added to the hcall which reflect new issues
found and new hardware mitigations.

This adds the link stack flush behaviour, link stack flush accelerated
instruction capability, and several L1D flush type behaviours (which are
now being specified as negative in order to simplify patched kernel
compatibility with older firmware).

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/ppc/spapr_hcall.c   | 5 +++++
 include/hw/ppc/spapr.h | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 7275d0bba1..f656620232 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1878,6 +1878,9 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU 
*cpu,
         behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
         break;
     case SPAPR_CAP_FIXED:
+        behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY;
+        behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS;
+        behaviour |= H_CPU_BEHAV_NO_STF_BARRIER;
         break;
     default: /* broken */
         assert(safe_cache == SPAPR_CAP_BROKEN);
@@ -1909,9 +1912,11 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU 
*cpu,
         break;
     case SPAPR_CAP_WORKAROUND:
         behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
+        behaviour |= H_CPU_BEHAV_FLUSH_LINK_STACK;
         if (count_cache_flush_assist) {
             characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST;
         }
+        /* Should have a way to enable BCCTR_LINK_FLUSH_ASSIST */
         break;
     default: /* broken */
         assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 7f40a158f4..883ac1db3c 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -395,10 +395,16 @@ struct SpaprMachineState {
 #define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
 #define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST           PPC_BIT(9)
+#define H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST      PPC_BIT(11)
+
 #define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
 #define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE           PPC_BIT(5)
+#define H_CPU_BEHAV_FLUSH_LINK_STACK            PPC_BIT(6)
+#define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY          PPC_BIT(7)
+#define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS        PPC_BIT(8)
+#define H_CPU_BEHAV_NO_STF_BARRIER              PPC_BIT(9)
 
 /* Each control block has to be on a 4K boundary */
 #define H_CB_ALIGNMENT     4096
-- 
2.23.0